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Mon, 11 Sep 2023 07:12:52 -0500 From: Vasant Hegde To: , CC: , , , , Vasant Hegde Subject: [PATCH v2 05/11] iommu/amd: Add support to enable/disable PASID feature Date: Mon, 11 Sep 2023 12:10:40 +0000 Message-ID: <20230911121046.1025732-6-vasant.hegde@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230911121046.1025732-1-vasant.hegde@amd.com> References: <20230911121046.1025732-1-vasant.hegde@amd.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A3:EE_|IA0PR12MB7649:EE_ X-MS-Office365-Filtering-Correlation-Id: 1c570a9a-6002-41a6-b792-08dbb2c06e15 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2023 12:12:55.2814 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1c570a9a-6002-41a6-b792-08dbb2c06e15 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7649 From: Suravee Suthikulpanit It seems iommu_dev_enable_feature(SVA) will be deprecated soon. Hence in this path we just return success. Instead we add necessary check during pasid bind to device. IN this path it checks whether device GCR3 table is setup or not. If not it will try to setup the GCR3. Signed-off-by: Suravee Suthikulpanit Co-developed-by: Wei Huang Signed-off-by: Wei Huang Co-developed-by: Vasant Hegde Signed-off-by: Vasant Hegde --- drivers/iommu/amd/amd_iommu.h | 2 ++ drivers/iommu/amd/iommu.c | 50 +++++++++++++++++++++++++++ drivers/iommu/amd/sva.c | 63 +++++++++++++++++++++++++++++++++++ 3 files changed, 115 insertions(+) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 7159b2610702..f7f576b8c8f6 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -43,6 +43,8 @@ bool amd_iommu_sva_supported(void); int amd_iommu_set_dev_pasid(struct iommu_domain *domain, struct device *dev, ioasid_t pasid); void amd_iommu_remove_dev_pasid(struct device *dev, ioasid_t pasid); +int amd_iommu_gcr3_init(struct iommu_dev_data *dev_data, int pasids); +void amd_iommu_gcr3_uninit(struct iommu_dev_data *dev_data); struct amd_iommu *get_amd_iommu(unsigned int idx); u8 amd_iommu_pc_get_max_banks(unsigned int idx); diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 94eec3dac8f6..5a9749cfe14e 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2162,6 +2162,50 @@ static void protection_domain_free(struct protection_domain *domain) kfree(domain); } +/******************************* + * PASID setup related helper functions + */ +static inline bool pdom_is_pt_mode(struct protection_domain *pdom) +{ + return (pdom->domain.type == IOMMU_DOMAIN_IDENTITY); +} + +static inline bool pdom_is_v2_pgtbl_mode(struct protection_domain *pdom) +{ + return (pdom->iop.pgd != NULL); +} + +int amd_iommu_gcr3_init(struct iommu_dev_data *dev_data, int pasids) +{ + struct protection_domain *pdom = dev_data->domain; + int ret = 0; + + lockdep_assert_held(&dev_data->lock); + + /* + * We cannot support PASID w/ existing v1 page table in the same domain + * since it will be nested. However, existing domain w/ v2 page table + * can be used for PASID. + */ + if (pdom->pd_mode == PD_MODE_V1) + return -EOPNOTSUPP; + + /* Allocate GCR3 table */ + if (pdom_is_pt_mode(dev_data->domain)) + ret = setup_gcr3_table(dev_data, pasids); + + return ret; +} + +void amd_iommu_gcr3_uninit(struct iommu_dev_data *dev_data) +{ + lockdep_assert_held(&dev_data->lock); + + /* Free GCR3 table */ + if (pdom_is_pt_mode(dev_data->domain)) + free_gcr3_table(dev_data); +} + static int protection_domain_init_v1(struct protection_domain *domain, int mode) { u64 *pt_root = NULL; @@ -2579,6 +2623,9 @@ static int amd_iommu_dev_enable_feature(struct device *dev, int ret; switch (feat) { + case IOMMU_DEV_FEAT_SVA: + ret = 0; + break; default: ret = -EINVAL; break; @@ -2592,6 +2639,9 @@ static int amd_iommu_dev_disable_feature(struct device *dev, int ret; switch (feat) { + case IOMMU_DEV_FEAT_SVA: + ret = 0; + break; default: ret = -EINVAL; break; diff --git a/drivers/iommu/amd/sva.c b/drivers/iommu/amd/sva.c index d18dc3f676b9..4cf1fb7864c4 100644 --- a/drivers/iommu/amd/sva.c +++ b/drivers/iommu/amd/sva.c @@ -12,6 +12,60 @@ #include "amd_iommu.h" +static inline bool is_pasid_enabled(struct iommu_dev_data *dev_data) +{ + if (dev_data->gcr3_info.gcr3_tbl != NULL && + dev_data->gcr3_info.pasid_cnt != 0) + return true; + + return false; +} + +static int amd_iommu_pasid_enable(struct iommu_dev_data *dev_data) +{ + struct device *dev = dev_data->dev; + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(&dev_data->lock, flags); + + if (dev_data->gcr3_info.gcr3_tbl != NULL && + dev_data->gcr3_info.pasid_cnt != 0) + goto out; + + if (!amd_iommu_sva_supported()) { + ret = -ENODEV; + goto out; + } + + if (!dev_data->pasid_enabled) { + ret = -EINVAL; + goto out; + } + + ret = amd_iommu_gcr3_init(dev_data, dev->iommu->max_pasids); + +out: + spin_unlock_irqrestore(&dev_data->lock, flags); + return ret; +} + +static void amd_iommu_pasid_disable(struct iommu_dev_data *dev_data) +{ + unsigned long flags; + + spin_lock_irqsave(&dev_data->lock, flags); + + if (dev_data->gcr3_info.gcr3_tbl == NULL) + return; + + if (dev_data->gcr3_info.pasid_cnt != 0) + return; + + amd_iommu_gcr3_uninit(dev_data); + spin_unlock_irqrestore(&dev_data->lock, flags); +} + static void sva_mn_invalidate_range(struct mmu_notifier *mn, struct mm_struct *mm, unsigned long start, unsigned long end) @@ -60,6 +114,13 @@ int amd_iommu_set_dev_pasid(struct iommu_domain *domain, /* Use SVA protection domain lock */ spin_lock_irqsave(&sva_pdom->lock, flags); + /* Make sure PASID is enabled */ + if (!is_pasid_enabled(dev_data)) { + ret = amd_iommu_pasid_enable(dev_data); + if (ret) + goto out; + } + /* Add PASID to protection domain pasid list */ pasid_data = kzalloc(sizeof(*pasid_data), GFP_KERNEL); if (pasid_data == NULL) { @@ -151,6 +212,8 @@ void amd_iommu_remove_dev_pasid(struct device *dev, ioasid_t pasid) /* Update GCR3 table and flush IOTLB */ amd_iommu_clear_gcr3(dev_data, pasid); + amd_iommu_pasid_disable(dev_data); + spin_unlock_irqrestore(&sva_pdom->lock, flags); if (list_empty(&sva_pdom->pasid_list)) -- 2.31.1