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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by MWH0EPF000971E4.mail.protection.outlook.com (10.167.243.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6838.14 via Frontend Transport; Fri, 6 Oct 2023 10:18:48 +0000 Received: from kali.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 6 Oct 2023 05:18:45 -0500 From: Vasant Hegde To: , CC: , Vasant Hegde Subject: [PATCH v1 07/13] iommu/amd: Consolidate device IOTLB flush code Date: Fri, 6 Oct 2023 10:16:18 +0000 Message-ID: <20231006101624.5912-8-vasant.hegde@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231006101624.5912-1-vasant.hegde@amd.com> References: <20231006101624.5912-1-vasant.hegde@amd.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E4:EE_|PH8PR12MB7375:EE_ X-MS-Office365-Filtering-Correlation-Id: 1b244ff3-8376-4645-8e24-08dbc655a163 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Oct 2023 10:18:48.3670 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1b244ff3-8376-4645-8e24-08dbc655a163 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7375 Currently we have separate code path to flush device IOTLB for host and guest page table (PASID table). Consolidate device IOTLB flush code in device_flush_iotlb_range(). Introduce helper function to find page table mode, decide whether to flush host/guest page table. Finally rename device_flush_iotlb() -> device_flush_iotlb_range(). Signed-off-by: Vasant Hegde --- drivers/iommu/amd/iommu.c | 33 +++++++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 2e7360fbc3c4..9a7f0f571862 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -83,6 +83,22 @@ static void detach_device(struct device *dev); * ****************************************************************************/ +/* + * For invalidation request without PASID, get the pasid based on + * domain page table mode. + */ +static inline ioasid_t pdom_get_default_pasid(struct protection_domain *pdom) +{ + return (pdom && (pdom->flags & PD_IOMMUV2_MASK)) ? + IOMMU_NO_PASID : IOMMU_PASID_INVALID; +} + +/* Used to select host/guest page table for invalidation */ +static inline bool is_pasid_valid(ioasid_t pasid) +{ + return (pasid != IOMMU_PASID_INVALID) ? true : false; +} + static inline int get_acpihid_device_id(struct device *dev, struct acpihid_map_entry **entry) { @@ -1380,12 +1396,13 @@ void amd_iommu_flush_all_caches(struct amd_iommu *iommu) /* * Command send function for flushing on-device TLB */ -static int device_flush_iotlb(struct iommu_dev_data *dev_data, - u64 address, size_t size) +static int device_flush_iotlb_range(struct iommu_dev_data *dev_data, + ioasid_t pasid, u64 address, size_t size) { struct amd_iommu *iommu; struct iommu_cmd cmd; int qdep; + bool gn = is_pasid_valid(pasid); qdep = dev_data->ats_qdep; iommu = rlookup_amd_iommu(dev_data->dev); @@ -1393,7 +1410,7 @@ static int device_flush_iotlb(struct iommu_dev_data *dev_data, return -EINVAL; build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, - size, IOMMU_NO_PASID, false); + size, pasid, gn); return iommu_queue_command(iommu, &cmd); } @@ -1439,8 +1456,11 @@ static int device_flush_dte(struct iommu_dev_data *dev_data) return ret; } - if (dev_data->ats_enabled) - ret = device_flush_iotlb(dev_data, 0, ~0UL); + if (dev_data->ats_enabled) { + ioasid_t pasid = pdom_get_default_pasid(dev_data->domain); + + ret = device_flush_iotlb_range(dev_data, pasid, 0, ~0UL); + } return ret; } @@ -1476,7 +1496,8 @@ static void __domain_flush_pages(struct protection_domain *domain, if (!dev_data->ats_enabled) continue; - ret |= device_flush_iotlb(dev_data, address, size); + ret |= device_flush_iotlb_range(dev_data, IOMMU_PASID_INVALID, + address, size); } WARN_ON(ret); -- 2.31.1