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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF00026369.mail.protection.outlook.com (10.167.241.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6838.22 via Frontend Transport; Fri, 13 Oct 2023 15:21:26 +0000 Received: from kali.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 13 Oct 2023 10:21:23 -0500 From: Vasant Hegde To: , CC: , , , , Vasant Hegde Subject: [PATCH v3 12/13] iommu/amd: Refactor GCR3 table helper functions Date: Fri, 13 Oct 2023 15:16:51 +0000 Message-ID: <20231013151652.6008-13-vasant.hegde@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013151652.6008-1-vasant.hegde@amd.com> References: <20231013151652.6008-1-vasant.hegde@amd.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00026369:EE_|BL1PR12MB5352:EE_ X-MS-Office365-Filtering-Correlation-Id: 2938220f-9684-4b59-5815-08dbcc001182 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2023 15:21:26.8097 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2938220f-9684-4b59-5815-08dbcc001182 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00026369.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5352 From: Suravee Suthikulpanit To use the new per-device struct gcr3_tbl_info. Also modify set_dte_entry() to use new per device GCR3 table. Signed-off-by: Suravee Suthikulpanit Co-developed-by: Vasant Hegde Signed-off-by: Vasant Hegde --- drivers/iommu/amd/iommu.c | 57 +++++++++++++++++++++++++-------------- 1 file changed, 37 insertions(+), 20 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 302ae7ed6d7c..988341ec499d 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1801,16 +1801,26 @@ static void free_gcr3_tbl_level2(u64 *tbl) } } -static void free_gcr3_table(struct protection_domain *domain) +static void free_gcr3_table(struct iommu_dev_data *dev_data) { - if (domain->glx == 2) - free_gcr3_tbl_level2(domain->gcr3_tbl); - else if (domain->glx == 1) - free_gcr3_tbl_level1(domain->gcr3_tbl); + struct gcr3_tbl_info *gcr3_info = &dev_data->gcr3_info; + struct amd_iommu *iommu = get_amd_iommu_from_dev(dev_data->dev); + + if (gcr3_info->glx == 2) + free_gcr3_tbl_level2(gcr3_info->gcr3_tbl); + else if (gcr3_info->glx == 1) + free_gcr3_tbl_level1(gcr3_info->gcr3_tbl); else - BUG_ON(domain->glx != 0); + WARN_ON_ONCE(gcr3_info->glx != 0); + + gcr3_info->glx = 0; + + set_dte_entry(iommu, dev_data); + clone_aliases(iommu, dev_data->dev); + device_flush_dte(dev_data); - free_page((unsigned long)domain->gcr3_tbl); + free_page((unsigned long)gcr3_info->gcr3_tbl); + gcr3_info->gcr3_tbl = NULL; } /* @@ -1829,22 +1839,28 @@ static int get_gcr3_levels(int pasids) return levels ? (DIV_ROUND_UP(levels, 9) - 1) : levels; } -/* Note: This function expects iommu_domain->lock to be held prior calling the function. */ -static int setup_gcr3_table(struct protection_domain *domain, int pasids) +static int setup_gcr3_table(struct iommu_dev_data *dev_data, int pasids) { + struct gcr3_tbl_info *gcr3_info = &dev_data->gcr3_info; + struct amd_iommu *iommu = get_amd_iommu_from_dev(dev_data->dev); int levels = get_gcr3_levels(pasids); if (levels > amd_iommu_max_glx_val) return -EINVAL; - domain->gcr3_tbl = alloc_pgtable_page(domain->nid, GFP_ATOMIC); - if (domain->gcr3_tbl == NULL) + if (gcr3_info->gcr3_tbl) + return -EBUSY; + + gcr3_info->gcr3_tbl = alloc_pgtable_page(dev_to_node(dev_data->dev), + GFP_ATOMIC); + if (gcr3_info->gcr3_tbl == NULL) return -ENOMEM; - domain->glx = levels; - domain->flags |= PD_IOMMUV2_MASK; + gcr3_info->glx = levels; - amd_iommu_domain_update(domain); + set_dte_entry(iommu, dev_data); + clone_aliases(iommu, dev_data->dev); + device_flush_dte(dev_data); return 0; } @@ -1960,6 +1976,7 @@ static void set_dte_entry(struct amd_iommu *iommu, u16 domid; struct protection_domain *domain = dev_data->domain; struct dev_table_entry *dev_table = get_dev_table(iommu); + struct gcr3_tbl_info *gcr3_info = &dev_data->gcr3_info; if (domain_id_is_per_dev(domain)) domid = dev_data->domid; @@ -1989,9 +2006,9 @@ static void set_dte_entry(struct amd_iommu *iommu, if (dev_data->ppr) pte_root |= 1ULL << DEV_ENTRY_PPR; - if (domain->flags & PD_IOMMUV2_MASK) { - u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl); - u64 glx = domain->glx; + if (gcr3_info && gcr3_info->gcr3_tbl) { + u64 gcr3 = iommu_virt_to_phys(gcr3_info->gcr3_tbl); + u64 glx = gcr3_info->glx; u64 tmp; pte_root |= DTE_FLAG_GV; @@ -2019,7 +2036,7 @@ static void set_dte_entry(struct amd_iommu *iommu, ((u64)GUEST_PGTABLE_5_LEVEL << DTE_GPT_LEVEL_SHIFT); } - if (domain->flags & PD_GIOV_MASK) + if (gcr3_info->giov) pte_root |= DTE_FLAG_GIOV; } @@ -2066,7 +2083,7 @@ static int _init_gcr3_tbl(struct iommu_dev_data *dev_data) * By default, setup GCR3 table to support MAX PASIDs * support by the IOMMU HW. */ - return setup_gcr3_table(dev_data->domain, -1); + return setup_gcr3_table(dev_data, -1); } static inline void _destroy_gcr3_tbl(struct iommu_dev_data *dev_data) @@ -2074,7 +2091,7 @@ static inline void _destroy_gcr3_tbl(struct iommu_dev_data *dev_data) struct gcr3_tbl_info *gcr3_info = &dev_data->gcr3_info; gcr3_info->giov = false; - free_gcr3_table(dev_data->domain); + free_gcr3_table(dev_data); } static int do_attach(struct iommu_dev_data *dev_data, -- 2.31.1