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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by MN1PEPF0000F0E3.mail.protection.outlook.com (10.167.242.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6838.22 via Frontend Transport; Mon, 16 Oct 2023 10:45:33 +0000 Received: from kali.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 16 Oct 2023 05:45:30 -0500 From: Vasant Hegde To: , CC: , , , , Vasant Hegde Subject: [PATCH v3 03/12] iommu/amd: Introduce per device DTE update function Date: Mon, 16 Oct 2023 10:43:42 +0000 Message-ID: <20231016104351.5749-4-vasant.hegde@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231016104351.5749-1-vasant.hegde@amd.com> References: <20231016104351.5749-1-vasant.hegde@amd.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E3:EE_|DM4PR12MB5311:EE_ X-MS-Office365-Filtering-Correlation-Id: 5b66b530-c3d2-49a4-6527-08dbce350632 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2023 10:45:33.5142 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5b66b530-c3d2-49a4-6527-08dbce350632 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5311 Consolidate per device update and flush logic into separate function. Also make it as global function as it will be used in subsequent series to update the DTE. Signed-off-by: Vasant Hegde --- drivers/iommu/amd/amd_iommu.h | 1 + drivers/iommu/amd/iommu.c | 40 +++++++++++++++++++++-------------- 2 files changed, 25 insertions(+), 16 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 0df0cb03329c..e3c7b99977c5 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -65,6 +65,7 @@ int amd_iommu_clear_gcr3(struct iommu_dev_data *dev_data, ioasid_t pasid); void amd_iommu_flush_all_caches(struct amd_iommu *iommu); void amd_iommu_update_and_flush_device_table(struct protection_domain *domain); void amd_iommu_domain_update(struct protection_domain *domain); +void amd_iommu_dev_update_dte(struct iommu_dev_data *dev_data, bool set); void amd_iommu_domain_flush_complete(struct protection_domain *domain); void amd_iommu_domain_flush_pages(struct protection_domain *pdom, u64 address, size_t size); diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 8e5d1dcc50dc..39acf98e45dd 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -79,6 +79,7 @@ static void detach_device(struct device *dev); static void set_dte_entry(struct amd_iommu *iommu, struct iommu_dev_data *dev_data); +static void clear_dte_entry(struct amd_iommu *iommu, u16 devid); /**************************************************************************** * @@ -1679,6 +1680,24 @@ static void domain_flush_np_cache(struct protection_domain *domain, } +/* Update and flush DTE for the given device */ +void amd_iommu_dev_update_dte(struct iommu_dev_data *dev_data, bool set) +{ + struct amd_iommu *iommu = get_amd_iommu_from_dev(dev_data->dev); + + if (!iommu) + return; + + if (set) + set_dte_entry(iommu, dev_data); + else + clear_dte_entry(iommu, dev_data->devid); + + clone_aliases(iommu, dev_data->dev); + + device_flush_dte(dev_data); +} + /* * This function flushes the DTEs for all devices in domain */ @@ -1804,7 +1823,6 @@ static void free_gcr3_tbl_level2(u64 *tbl) static void free_gcr3_table(struct iommu_dev_data *dev_data) { struct gcr3_tbl_info *gcr3_info = &dev_data->gcr3_info; - struct amd_iommu *iommu = get_amd_iommu_from_dev(dev_data->dev); if (gcr3_info->glx == 2) free_gcr3_tbl_level2(gcr3_info->gcr3_tbl); @@ -1815,9 +1833,7 @@ static void free_gcr3_table(struct iommu_dev_data *dev_data) gcr3_info->glx = 0; - set_dte_entry(iommu, dev_data); - clone_aliases(iommu, dev_data->dev); - device_flush_dte(dev_data); + amd_iommu_dev_update_dte(dev_data, true); free_page((unsigned long)gcr3_info->gcr3_tbl); gcr3_info->gcr3_tbl = NULL; @@ -1842,7 +1858,6 @@ static int get_gcr3_levels(int pasids) static int setup_gcr3_table(struct iommu_dev_data *dev_data, int pasids) { struct gcr3_tbl_info *gcr3_info = &dev_data->gcr3_info; - struct amd_iommu *iommu = get_amd_iommu_from_dev(dev_data->dev); int levels = get_gcr3_levels(pasids); if (levels > amd_iommu_max_glx_val) @@ -1858,9 +1873,7 @@ static int setup_gcr3_table(struct iommu_dev_data *dev_data, int pasids) gcr3_info->glx = levels; - set_dte_entry(iommu, dev_data); - clone_aliases(iommu, dev_data->dev); - device_flush_dte(dev_data); + amd_iommu_dev_update_dte(dev_data, true); return 0; } @@ -2138,10 +2151,7 @@ static int do_attach(struct iommu_dev_data *dev_data, } /* Update device table */ - set_dte_entry(iommu, dev_data); - clone_aliases(iommu, dev_data->dev); - - device_flush_dte(dev_data); + amd_iommu_dev_update_dte(dev_data, true); return ret; } @@ -2164,11 +2174,9 @@ static void do_detach(struct iommu_dev_data *dev_data) /* Update data structures */ dev_data->domain = NULL; list_del(&dev_data->list); - clear_dte_entry(iommu, dev_data->devid); - clone_aliases(iommu, dev_data->dev); - /* Flush the DTE entry */ - device_flush_dte(dev_data); + /* Clear DTE and flush the entry */ + amd_iommu_dev_update_dte(dev_data, false); /* Flush IOTLB and wait for the flushes to finish */ amd_iommu_domain_flush_all(domain); -- 2.31.1