Re: [PATCH] iommu/arm-smmu-v3: disable stall for quiet_cd

[Jason Gunthorpe <jgg@nvidia.com>]

On Wed, Dec 06, 2023 at 08:57:27AM +0800, Zhangfei Gao wrote:
> From: Wenkai Lin <linwenkai6@hisilicon.com>
> 
> In the stall model, invalid transactions were expected to be
> stalled and aborted by the IOPF handler.
> 
> However, when killing a test case with a huge amount of data, the
> accelerator streamline can not stop until all data is consumed
> even if the page fault handler reports errors. As a result, the
> kill may take a long time, about 10 seconds with numerous iopf
> interrupts.
> 
> So disable stall for quiet_cd in the non-force stall model, since
> force stall model (STALL_MODEL==0b10) requires CD.S must be 1.

I think this force-stall thing should get a closer look, it doesn't
look completely implemented and what does it mean for, eg, non-SVA
domains attached to the device (as we now support with S2 and soon
with PASID)

The manual says:

0b10 Stall is forced (all faults eligible to stall cause stall),
     STE.S2S and CD.S must be 1.

And there is a note:

 Note: For faulting transactions that are associated with client
 devices that have been configured to stall, but where
 the system has not explicitly advertised the client devices to be
 usable with the stall model, Arm recommends for
 software to expect that events might be recorded with Stall == 0.

Which makes it seem like it isn't actually "force" per-say, but
something else.

I notice the driver never sets STE.S2S, and it isn't entirely clear
what software should even do for a standard non-faulting domain where
non-present means failure? Take the fault event and always respond
with failure? What is the purpose?

Aside from that the change looks OK to me:

Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>

Jason