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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000042A8.mail.protection.outlook.com (10.167.243.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7091.26 via Frontend Transport; Tue, 12 Dec 2023 08:52:53 +0000 Received: from kali.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 12 Dec 2023 02:52:49 -0600 From: Vasant Hegde To: , CC: , , , , Vasant Hegde Subject: [PATCH v4 00/16] iommu/amd: SVA Support (part 3) - refactor support for GCR3 table Date: Tue, 12 Dec 2023 08:52:08 +0000 Message-ID: <20231212085224.6985-1-vasant.hegde@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042A8:EE_|SA3PR12MB8764:EE_ X-MS-Office365-Filtering-Correlation-Id: d98f54f3-34d2-462d-6119-08dbfaefba3c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2023 08:52:53.0141 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d98f54f3-34d2-462d-6119-08dbfaefba3c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8764 This is part 3 of the 4-part series to introduce Share Virtual Address (SVA) support, which focuses on refactoring GCR3 table. This moves GCR3 related information from protection domain structure to iommu_dev_data (per device) structure. It contains the following enhancements: * Patch 1 - 3: Cleanup and introduce helper function * Patch 4 - 13: Introduce per device GCR3 table, per device domain ID, invalidation based on per device and code refactoring * Patch 14 - 16: Remove unused variable, rearrange functions to make it easy to maintain This patch series is based on top of iommu/next branch (commit bd19c7637024). This is also available at github : https://github.com/AMDESE/linux/tree/iommu_sva_part3_v4_v6.7_rc5 Thanks Jason for reviewing previous versions and providing valuable feedbacks. Changes from v3 -> v4: - Added new patch to enable IOMMU GT feature early - Fixed dirty tracking path to use get_amd_iommu_from_dev() - Fixed duplicate flush issue in do_attach() path - Removed gcr3_info->giov variable. Instead we use domain page table mode to decide DTE[GIOV] bit. - Free gcr3_table before calling set_dte_entry (otherwise there is a possibility of its setting up gcr3 table with glx 0) - Adjusted gfp_t flag for GCR3 table allocation (GPF_ATOMIC -> GFP_KERNEL) - Moved below patches from invalidation improvement series to this series * Remove unused flush_pasid() related functions (Originally it was part of Invalidation improvement series, I had to push it to this series as set_gcr3() was still using __amd_iommu_flush_tlb()). * Added patch to Rearrange device flush code v3 : https://lore.kernel.org/linux-iommu/20231013151652.6008-1-vasant.hegde@amd.com/T/#t Changes from v2 -> v3: - Dropped "iommu/amd: Use struct protection_domain in helper functions" as flush related functions are already fixed and set_gcr3 related functions is reworked in this series. - Removed moving to_pdomain() function from this series. It will be introduced in SVA series where it will be used. - Added per device domain ID and per device invalidation functions - Added functions to flush TLB for the given device - Added Review-by tags v2 : https://lore.kernel.org/linux-iommu/20230816174031.634453-1-vasant.hegde@amd.com/T/#t Changes from v1 - v2: - Dropped iommu_v2 module related support as newly introduced Part2 removed iommu_v2 module. - Moved Patch 'Use struct protection_domain in helper functions' from Part1 to Part3 - Updated get_amd_iommu_from_dev() to retrieve iommu from device structure - Removed 'PD_MODE_PT' v1 : https://lore.kernel.org/linux-iommu/20230808100232.5977-1-vasant.hegde@amd.com/T/#t Suravee Suthikulpanit (8): iommu/amd: Introduce get_amd_iommu_from_dev() iommu/amd: Introduce struct protection_domain.pd_mode iommu/amd: Introduce per-device GCR3 table iommu/amd: Refactor helper function for setting / clearing GCR3 iommu/amd: Refactor attaching / detaching device functions iommu/amd: Refactor protection_domain helper functions iommu/amd: Refactor GCR3 table helper functions iommu/amd: Remove unused GCR3 table parameters from struct protection_domain Vasant Hegde (8): iommu/amd: Pass struct iommu_dev_data to set_dte_entry() iommu/amd: Enable Guest Translation before registering devices iommu/amd: Use protection_domain.flags to check page table mode iommu/amd: Introduce per-device domain ID to workaround potential TLB aliasing issue iommu/amd: Add support for device based TLB invalidation iommu/amd: Rearrange GCR3 table setup code iommu/amd: Remove unused flush pasid functions iommu/amd: Rearrange device flush code drivers/iommu/amd/amd_iommu.h | 25 +- drivers/iommu/amd/amd_iommu_types.h | 27 +- drivers/iommu/amd/init.c | 6 +- drivers/iommu/amd/io_pgtable_v2.c | 21 +- drivers/iommu/amd/iommu.c | 646 ++++++++++++++-------------- include/linux/iommu.h | 13 + 6 files changed, 371 insertions(+), 367 deletions(-) -- 2.31.1