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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by MWH0EPF000971E7.mail.protection.outlook.com (10.167.243.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7113.14 via Frontend Transport; Thu, 21 Dec 2023 11:16:20 +0000 Received: from kali.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Thu, 21 Dec 2023 05:16:17 -0600 From: Vasant Hegde To: , CC: , , , , Vasant Hegde Subject: [PATCH v4 00/14] iommu/amd: SVA Support (Part 4) - SVA and IOPF Date: Thu, 21 Dec 2023 11:15:44 +0000 Message-ID: <20231221111558.64652-1-vasant.hegde@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E7:EE_|BL3PR12MB6548:EE_ X-MS-Office365-Filtering-Correlation-Id: 4fad1a97-11bc-48ef-cc73-08dc02164286 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Dec 2023 11:16:20.7028 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4fad1a97-11bc-48ef-cc73-08dc02164286 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6548 This is part 4 of the 4-part series to introduce Share Virtual Address (SVA) support for devices, which can support PCI ATS, PASID and PRI capabilities. These devices are referred to as SVA-capable devices in this series. It contains the following enhancements: * Patch 1 - 3: Rename, add support to enable/disable features, update DTE etc. * Patch 4 - 10: Add IOPF support * Patch 11 - 14: Introduce SVA support This patch series is based on top of SVA Part 3 v4. https://lore.kernel.org/linux-iommu/20231212085224.6985-1-vasant.hegde@amd.com/T/#t Also depends on : 1) Baolu's IOPF improvement https://lore.kernel.org/linux-iommu/cbfbe969-1a92-52bf-f00c-3fb89feefd66@linux.intel.com/ This is also available at github : https://github.com/AMDESE/linux/tree/iommu_sva_part4_v4_v6.7_rc5 Thanks everyone who reviewed previous version and provided valuable feedbacks. Changes from v3 -> v4: - Moved amd_iommu_dev_update_dte() after set/clear_dte() so that we can avoid forward declaration - Dropped "iommu/amd: Do not override PASID entry in GCR3 table" - Added patch to fix PPR interrupt processing logic - Renamed enable_iommus_v2() -> enable_iommus_ppr() - Added ops->domain_alloc_sva() - Added domain_alloc_sva() support and reorganize SVA patches - In error path iommu_call_iopf_notifier() calls amd_iommu_complete_ppr() instead of amd_iommu_page_response() v3: https://lore.kernel.org/linux-iommu/20231016104351.5749-1-vasant.hegde@amd.com/T/#t Changes from v2 -> v3: - Rename sva.c -> pasid.c - Changed amd_iommu_sva_supported() -> amd_iommu_pasid_supported() - Added patch to update/flush DTE - Rework part of SVA support - Move IOPF enablement to PASID bind time v2: https://lore.kernel.org/linux-iommu/20230911121046.1025732-1-vasant.hegde@amd.com/T/#u Changes from v1 -> v2: - Added new patch to fix PASID override issue in GCR3 table - Complete rework of SVA code on top of Tina's SVA series. - Rework SVA enable code - Reworked IOPF handler code on top of Baolu's IOPF improvement series. v1: https://lore.kernel.org/linux-iommu/20230823140415.729050-1-vasant.hegde@amd.com/T/#t Thank you, Vasant / Suravee Jason Gunthorpe (1): iommu: Add ops->domain_alloc_sva() Suravee Suthikulpanit (5): iommu/amd: Move PPR-related functions into ppr.c iommu/amd: Define per-IOMMU iopf_queue iommu/amd: Add support for page response iommu/amd: Introduce logic to enable/disable IOPF iommu/amd: Add GCR3 [un]initialization function Vasant Hegde (5): iommu/amd: Rename amd_iommu_v2_supported() as amd_iommu_pasid_supported() iommu/amd: Introduce per device DTE update function iommu/amd: Fix PPR interrupt processing logic iommu/amd: Initial SVA support for AMD IOMMU iommu/amd: Add SVA domain support Wei Huang (3): iommu/amd: Add support for enabling/disabling IOMMU features iommu/amd: Add support for add/remove device for IOPF iommu/amd: Add IO page fault notifier handler drivers/iommu/amd/Kconfig | 2 + drivers/iommu/amd/Makefile | 2 +- drivers/iommu/amd/amd_iommu.h | 51 +++- drivers/iommu/amd/amd_iommu_types.h | 27 +++ drivers/iommu/amd/init.c | 79 ++---- drivers/iommu/amd/iommu.c | 182 ++++++++------ drivers/iommu/amd/pasid.c | 277 +++++++++++++++++++++ drivers/iommu/amd/ppr.c | 362 ++++++++++++++++++++++++++++ drivers/iommu/iommu-sva.c | 17 +- include/linux/iommu.h | 3 + 10 files changed, 862 insertions(+), 140 deletions(-) create mode 100644 drivers/iommu/amd/pasid.c create mode 100644 drivers/iommu/amd/ppr.c -- 2.31.1