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[142.68.80.239]) by smtp.gmail.com with ESMTPSA id z13-20020a05620a100d00b00783f290c8f2sm749512qkj.9.2024.02.02.07.17.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Feb 2024 07:17:39 -0800 (PST) Received: from jgg by wakko with local (Exim 4.95) (envelope-from ) id 1rVvIQ-00AwAT-KQ; Fri, 02 Feb 2024 11:17:38 -0400 Date: Fri, 2 Feb 2024 11:17:38 -0400 From: Jason Gunthorpe To: Vasant Hegde Cc: iommu@lists.linux.dev, joro@8bytes.org, suravee.suthikulpanit@amd.com, wei.huang2@amd.com, jsnitsel@redhat.com Subject: Re: [PATCH v5 11/14] iommu/amd: Add GCR3 [un]initialization function Message-ID: <20240202151738.GU50608@ziepe.ca> References: <20240118073339.6978-1-vasant.hegde@amd.com> <20240118073339.6978-12-vasant.hegde@amd.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240118073339.6978-12-vasant.hegde@amd.com> On Thu, Jan 18, 2024 at 07:33:36AM +0000, Vasant Hegde wrote: > From: Suravee Suthikulpanit > > These functions are used in PASID to device bind path. In this path > it checks whether device GCR3 table is setup or not. If not it will > setup GCR3 table. > > Also in attach device path change default GCR3 table to use MAX > supported PASIDs. Ideally it should use 1 level PASID table as its > using PASID zero only. But we don't have support to extend PASID table > yet. We will fix this later. > > Signed-off-by: Suravee Suthikulpanit > Co-developed-by: Vasant Hegde > Signed-off-by: Vasant Hegde > --- > drivers/iommu/amd/amd_iommu.h | 3 ++ > drivers/iommu/amd/iommu.c | 52 +++++++++++++++++++++++++++++++++-- > 2 files changed, 53 insertions(+), 2 deletions(-) > > diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h > index d5e6315ef9dd..2d099c54b941 100644 > --- a/drivers/iommu/amd/amd_iommu.h > +++ b/drivers/iommu/amd/amd_iommu.h > @@ -44,7 +44,10 @@ extern int amd_iommu_guest_ir; > extern enum io_pgtable_fmt amd_iommu_pgtable; > extern int amd_iommu_gpt_level; > > +/* SVA/PASID */ > bool amd_iommu_pasid_supported(void); > +int amd_iommu_gcr3_init(struct iommu_dev_data *dev_data, ioasid_t pasids); > +void amd_iommu_gcr3_uninit(struct iommu_dev_data *dev_data); > > /* IOPF */ > int amd_iommu_iopf_init(struct amd_iommu *iommu); > diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c > index 36a5458a7946..6f5900333946 100644 > --- a/drivers/iommu/amd/iommu.c > +++ b/drivers/iommu/amd/iommu.c > @@ -93,6 +93,11 @@ static inline bool pdom_is_v2_pgtbl_mode(struct protection_domain *pdom) > return (pdom && (pdom->pd_mode == PD_MODE_V2)); > } > > +static inline bool pdom_is_in_pt_mode(struct protection_domain *pdom) > +{ > + return (pdom->domain.type == IOMMU_DOMAIN_IDENTITY); > +} Why? And what about blocking someday? Just use dev_data->gcr3_info.gcr3_tbl == NULL to indicate if GCR3 is loaded or not? > /* > * Allocate per device domain ID when using V2 page table > */ > @@ -1837,6 +1842,46 @@ int amd_iommu_clear_gcr3(struct iommu_dev_data *dev_data, ioasid_t pasid) > return ret; > } > > +int amd_iommu_gcr3_init(struct iommu_dev_data *dev_data, ioasid_t pasids) > +{ > + struct protection_domain *pdom = dev_data->domain; > + int ret = 0; > + > + lockdep_assert_held(&dev_data->lock); > + > + /* > + * We cannot support PASID w/ existing v1 page table in the same domain > + * since it will be nested. However, existing domain w/ v2 page table > + * can be used for PASID. > + */ > + if (!pdom_is_v2_pgtbl_mode(pdom) && !pdom_is_in_pt_mode(pdom)) > + return -EOPNOTSUPP; Put the test directly in the set dev pasid op and it should be more like if (!dev_data->gcr3_info.gcr3_tbl && dev_data->domain->type & _IOMMU_DOMAIN_PAGING) return -EINVAL; And you need the mirroring test in alloc_dev to prevent changing the RID to things the driver does not yet support, I didn't notice that? > + /* Allocate GCR3 table */ > + if (pdom_is_in_pt_mode(pdom) && dev_data->gcr3_info.gcr3_tbl == NULL) { > + ret = setup_gcr3_table(&dev_data->gcr3_info, > + dev_to_node(dev_data->dev), pasids); > + > + /* Update device table */ > + amd_iommu_dev_update_dte(dev_data, true); > + } This shouldn't be any different from do_attach() > + > + return ret; success oritened flow please > +void amd_iommu_gcr3_uninit(struct iommu_dev_data *dev_data) > +{ > + lockdep_assert_held(&dev_data->lock); > + > + /* Free GCR3 table */ > + if (pdom_is_in_pt_mode(dev_data->domain)) { > + free_gcr3_table(&dev_data->gcr3_info); > + > + /* Update device table */ > + amd_iommu_dev_update_dte(dev_data, true); > + } > +} Is it really worth freeing it? > static void set_dte_entry(struct amd_iommu *iommu, > struct iommu_dev_data *dev_data) > { > @@ -1986,9 +2031,12 @@ static int do_attach(struct iommu_dev_data *dev_data, > > /* Init GCR3 table and update device table */ > if (domain->pd_mode == PD_MODE_V2) { > - /* By default, setup GCR3 table to support single PASID */ > + /* > + * By default, setup GCR3 table to support MAX PASIDs > + * supported by the IOMMU HW. > + */ > ret = setup_gcr3_table(&dev_data->gcr3_info, > - dev_to_node(dev_data->dev), 1); > + dev_to_node(dev_data->dev), -1); -1 should be dev->iommu->max_pasids, but better would be this specific device's max pasid size, cached from pci_max_pasids() Jason