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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000EE35.mail.protection.outlook.com (10.167.242.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7249.19 via Frontend Transport; Mon, 5 Feb 2024 11:56:35 +0000 Received: from kali.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Mon, 5 Feb 2024 05:56:31 -0600 From: Vasant Hegde To: , CC: , , , , Vasant Hegde Subject: [PATCH v7 00/17] iommu/amd: SVA Support (part 3) - refactor support for GCR3 table Date: Mon, 5 Feb 2024 11:55:58 +0000 Message-ID: <20240205115615.6053-1-vasant.hegde@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE35:EE_|SJ2PR12MB8133:EE_ X-MS-Office365-Filtering-Correlation-Id: ebe51b04-c41a-4e53-04a5-08dc264180c1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Feb 2024 11:56:35.3693 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ebe51b04-c41a-4e53-04a5-08dc264180c1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE35.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8133 This is part 3 of the 4-part series to introduce Share Virtual Address (SVA) support, which focuses on refactoring GCR3 table. This moves GCR3 related information from protection domain structure to iommu_dev_data (per device) structure. It contains the following enhancements: * Patch 1 - 3: Cleanup and introduce helper function * Patch 4 - 13: Introduce per device GCR3 table, invalidation based on per device and code refactoring. Also introduce iommu_group_mutex_assert. * Patch 14 - 16: Remove unused variable, rearrange functions to make it easy to maintain * Patch 17: Introduce per device domain ID. This patch series is based on top of iommu/next branch (commit d2d00e15808). This is also available at github : https://github.com/AMDESE/linux/tree/iommu_sva_part3_v7_v6.8_rc2 Thanks Jason for reviewing previous versions and providing valuable feedbacks. Changes from v6 -> v7: - Added Reviewed-by tags - Rebased on top of iommu/next branch - iommu: Introduce iommu_group_mutex_assert() Removed 'extern' from iommu_group_mutex_assert() declaration - iommu/amd: Refactor helper function for setting / clearing GCR3 Followed-success oriented flow - Minor update to patch 11/17 description v6: https://lore.kernel.org/linux-iommu/20240125121135.8217-1-vasant.hegde@amd.com/T/#t Changes from v5 -> v6: - Moved per-device-domain-ID patch to end - Added condition check for iommu_group_mutex_assert() - Moving per-device-domain-id allocation/free to setup_gcr3_table()/free_gcr3_table - Pass iommu to setup_gcr3_table instead of passing nid v5: https://lore.kernel.org/linux-iommu/20240116165335.6043-1-vasant.hegde@amd.com/T/#t Changes from v4 -> v5: - Added get_amd_iommu_from_dev_data() - pass gcr3_info instead of dev_data to setup/free_gcr3_table() - Added path to EXPORT iommu_group_mutex_assert - Moved dev_data->domid to gcr3_info->domid v4: https://lore.kernel.org/linux-iommu/20231212085224.6985-1-vasant.hegde@amd.com/T/#t Changes from v3 -> v4: - Added new patch to enable IOMMU GT feature early - Fixed dirty tracking path to use get_amd_iommu_from_dev() - Fixed duplicate flush issue in do_attach() path - Removed gcr3_info->giov variable. Instead we use domain page table mode to decide DTE[GIOV] bit. - Free gcr3_table before calling set_dte_entry (otherwise there is a possibility of its setting up gcr3 table with glx 0) - Adjusted gfp_t flag for GCR3 table allocation (GPF_ATOMIC -> GFP_KERNEL) - Moved below patches from invalidation improvement series to this series * Remove unused flush_pasid() related functions (Originally it was part of Invalidation improvement series, I had to push it to this series as set_gcr3() was still using __amd_iommu_flush_tlb()). * Added patch to Rearrange device flush code v3 : https://lore.kernel.org/linux-iommu/20231013151652.6008-1-vasant.hegde@amd.com/T/#t Changes from v2 -> v3: - Dropped "iommu/amd: Use struct protection_domain in helper functions" as flush related functions are already fixed and set_gcr3 related functions is reworked in this series. - Removed moving to_pdomain() function from this series. It will be introduced in SVA series where it will be used. - Added per device domain ID and per device invalidation functions - Added functions to flush TLB for the given device - Added Review-by tags v2 : https://lore.kernel.org/linux-iommu/20230816174031.634453-1-vasant.hegde@amd.com/T/#t Changes from v1 - v2: - Dropped iommu_v2 module related support as newly introduced Part2 removed iommu_v2 module. - Moved Patch 'Use struct protection_domain in helper functions' from Part1 to Part3 - Updated get_amd_iommu_from_dev() to retrieve iommu from device structure - Removed 'PD_MODE_PT' v1 : https://lore.kernel.org/linux-iommu/20230808100232.5977-1-vasant.hegde@amd.com/T/#t Thank you, Vasant / Suravee Suravee Suthikulpanit (8): iommu/amd: Introduce get_amd_iommu_from_dev() iommu/amd: Introduce struct protection_domain.pd_mode iommu/amd: Introduce per-device GCR3 table iommu/amd: Refactor helper function for setting / clearing GCR3 iommu/amd: Refactor attaching / detaching device functions iommu/amd: Refactor protection_domain helper functions iommu/amd: Refactor GCR3 table helper functions iommu/amd: Remove unused GCR3 table parameters from struct protection_domain Vasant Hegde (9): iommu/amd: Pass struct iommu_dev_data to set_dte_entry() iommu/amd: Enable Guest Translation before registering devices iommu/amd: Use protection_domain.flags to check page table mode iommu/amd: Add support for device based TLB invalidation iommu/amd: Rearrange GCR3 table setup code iommu: Introduce iommu_group_mutex_assert() iommu/amd: Remove unused flush pasid functions iommu/amd: Rearrange device flush code iommu/amd: Introduce per-device domain ID to fix potential TLB aliasing issue drivers/iommu/amd/amd_iommu.h | 29 +- drivers/iommu/amd/amd_iommu_types.h | 26 +- drivers/iommu/amd/init.c | 6 +- drivers/iommu/amd/io_pgtable_v2.c | 21 +- drivers/iommu/amd/iommu.c | 627 +++++++++++++--------------- drivers/iommu/iommu.c | 19 + include/linux/iommu.h | 24 ++ 7 files changed, 376 insertions(+), 376 deletions(-) -- 2.31.1