Linux IOMMU Development
 help / color / mirror / Atom feed
From: Vasant Hegde <vasant.hegde@amd.com>
To: <iommu@lists.linux.dev>, <joro@8bytes.org>
Cc: <suravee.suthikulpanit@amd.com>, <wei.huang2@amd.com>,
	<jsnitsel@redhat.com>, <jgg@ziepe.ca>,
	Vasant Hegde <vasant.hegde@amd.com>,
	Jason Gunthorpe <jgg@nvidia.com>
Subject: [PATCH v7 02/17] iommu/amd: Enable Guest Translation before registering devices
Date: Mon, 5 Feb 2024 11:56:00 +0000	[thread overview]
Message-ID: <20240205115615.6053-3-vasant.hegde@amd.com> (raw)
In-Reply-To: <20240205115615.6053-1-vasant.hegde@amd.com>

IOMMU Guest Translation (GT) feature needs to be enabled before
invalidating guest translations (CMD_INV_IOMMU_PAGES with GN=1).

Currently GT feature is enabled after setting up interrupt handler.
So far it was fine as we were not invalidating guest page table
before this point.

Upcoming series will introduce per device GCR3 table and it will
invalidate guest pages after configuring. Hence move GT feature
enablement to early_enable_iommu().

Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
---
 drivers/iommu/amd/init.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index c83bd0c2a1c9..959820ccfbcc 100644
--- a/drivers/iommu/amd/init.c
+++ b/drivers/iommu/amd/init.c
@@ -2769,6 +2769,7 @@ static void early_enable_iommu(struct amd_iommu *iommu)
 	iommu_enable_command_buffer(iommu);
 	iommu_enable_event_buffer(iommu);
 	iommu_set_exclusion_range(iommu);
+	iommu_enable_gt(iommu);
 	iommu_enable_ga(iommu);
 	iommu_enable_xt(iommu);
 	iommu_enable_irtcachedis(iommu);
@@ -2825,6 +2826,7 @@ static void early_enable_iommus(void)
 			iommu_disable_irtcachedis(iommu);
 			iommu_enable_command_buffer(iommu);
 			iommu_enable_event_buffer(iommu);
+			iommu_enable_gt(iommu);
 			iommu_enable_ga(iommu);
 			iommu_enable_xt(iommu);
 			iommu_enable_irtcachedis(iommu);
@@ -2838,10 +2840,8 @@ static void enable_iommus_v2(void)
 {
 	struct amd_iommu *iommu;
 
-	for_each_iommu(iommu) {
+	for_each_iommu(iommu)
 		iommu_enable_ppr_log(iommu);
-		iommu_enable_gt(iommu);
-	}
 }
 
 static void enable_iommus_vapic(void)
-- 
2.31.1


  parent reply	other threads:[~2024-02-05 11:57 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-05 11:55 [PATCH v7 00/17] iommu/amd: SVA Support (part 3) - refactor support for GCR3 table Vasant Hegde
2024-02-05 11:55 ` [PATCH v7 01/17] iommu/amd: Pass struct iommu_dev_data to set_dte_entry() Vasant Hegde
2024-02-05 11:56 ` Vasant Hegde [this message]
2024-02-05 11:56 ` [PATCH v7 03/17] iommu/amd: Introduce get_amd_iommu_from_dev() Vasant Hegde
2024-02-05 11:56 ` [PATCH v7 04/17] iommu/amd: Introduce struct protection_domain.pd_mode Vasant Hegde
2024-02-05 11:56 ` [PATCH v7 05/17] iommu/amd: Introduce per-device GCR3 table Vasant Hegde
2024-02-05 11:56 ` [PATCH v7 06/17] iommu/amd: Use protection_domain.flags to check page table mode Vasant Hegde
2024-02-05 11:56 ` [PATCH v7 07/17] iommu/amd: Add support for device based TLB invalidation Vasant Hegde
2024-02-05 11:56 ` [PATCH v7 08/17] iommu/amd: Rearrange GCR3 table setup code Vasant Hegde
2024-02-05 11:56 ` [PATCH v7 09/17] iommu: Introduce iommu_group_mutex_assert() Vasant Hegde
2024-02-05 11:56 ` [PATCH v7 10/17] iommu/amd: Refactor helper function for setting / clearing GCR3 Vasant Hegde
2024-02-05 11:56 ` [PATCH v7 11/17] iommu/amd: Refactor attaching / detaching device functions Vasant Hegde
2024-02-05 11:56 ` [PATCH v7 12/17] iommu/amd: Refactor protection_domain helper functions Vasant Hegde
2024-02-05 11:56 ` [PATCH v7 13/17] iommu/amd: Refactor GCR3 table " Vasant Hegde
2024-02-05 11:56 ` [PATCH v7 14/17] iommu/amd: Remove unused flush pasid functions Vasant Hegde
2024-02-05 11:56 ` [PATCH v7 15/17] iommu/amd: Rearrange device flush code Vasant Hegde
2024-02-05 11:56 ` [PATCH v7 16/17] iommu/amd: Remove unused GCR3 table parameters from struct protection_domain Vasant Hegde
2024-02-05 11:56 ` [PATCH v7 17/17] iommu/amd: Introduce per-device domain ID to fix potential TLB aliasing issue Vasant Hegde
2024-02-09 10:44 ` [PATCH v7 00/17] iommu/amd: SVA Support (part 3) - refactor support for GCR3 table Joerg Roedel

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20240205115615.6053-3-vasant.hegde@amd.com \
    --to=vasant.hegde@amd.com \
    --cc=iommu@lists.linux.dev \
    --cc=jgg@nvidia.com \
    --cc=jgg@ziepe.ca \
    --cc=joro@8bytes.org \
    --cc=jsnitsel@redhat.com \
    --cc=suravee.suthikulpanit@amd.com \
    --cc=wei.huang2@amd.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox