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Wed, 22 May 2024 07:43:20 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGqJHjQHAf8ioYQJxg3KTDvGvqncn/7PxrQwSaE3bVUPwOeK3bCtm4GVPxds6m+Fab6ef5A4w== X-Received: by 2002:a05:6e02:12e8:b0:36c:45bf:a8f0 with SMTP id e9e14a558f8ab-371fb91fe79mr24461105ab.25.1716389000614; Wed, 22 May 2024 07:43:20 -0700 (PDT) Received: from redhat.com ([38.15.36.11]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-37195389d91sm6333875ab.7.2024.05.22.07.43.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 May 2024 07:43:20 -0700 (PDT) Date: Wed, 22 May 2024 08:43:18 -0600 From: Alex Williamson To: Jason Gunthorpe Cc: "Tian, Kevin" , "Vetter, Daniel" , "Zhao, Yan Y" , "kvm@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "x86@kernel.org" , "iommu@lists.linux.dev" , "pbonzini@redhat.com" , "seanjc@google.com" , "dave.hansen@linux.intel.com" , "luto@kernel.org" , "peterz@infradead.org" , "tglx@linutronix.de" , "mingo@redhat.com" , "bp@alien8.de" , "hpa@zytor.com" , "corbet@lwn.net" , "joro@8bytes.org" , "will@kernel.org" , "robin.murphy@arm.com" , "baolu.lu@linux.intel.com" , "Liu, Yi L" Subject: Re: [PATCH 4/5] vfio/type1: Flush CPU caches on DMA pages in non-coherent domains Message-ID: <20240522084318.43e0dbb1.alex.williamson@redhat.com> In-Reply-To: <20240522122939.GT20229@nvidia.com> References: <20240516143159.0416d6c7.alex.williamson@redhat.com> <20240517171117.GB20229@nvidia.com> <20240521160714.GJ20229@nvidia.com> <20240521102123.7baaf85a.alex.williamson@redhat.com> <20240521163400.GK20229@nvidia.com> <20240521121945.7f144230.alex.williamson@redhat.com> <20240521183745.GP20229@nvidia.com> <20240522122939.GT20229@nvidia.com> X-Mailer: Claws Mail 4.2.0 (GTK 3.24.41; x86_64-redhat-linux-gnu) Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Wed, 22 May 2024 09:29:39 -0300 Jason Gunthorpe wrote: > On Wed, May 22, 2024 at 06:24:14AM +0000, Tian, Kevin wrote: > > > From: Jason Gunthorpe > > > Sent: Wednesday, May 22, 2024 2:38 AM > > > > > > On Tue, May 21, 2024 at 12:19:45PM -0600, Alex Williamson wrote: > > > > > I'm OK with this. If devices are insecure then they need quirks in > > > > > vfio to disclose their problems, we shouldn't punish everyone who > > > > > followed the spec because of some bad actors. > > > > > > > > > > But more broadly in a security engineered environment we can trust the > > > > > no-snoop bit to work properly. > > > > > > > > The spec has an interesting requirement on devices sending no-snoop > > > > transactions anyway (regarding PCI_EXP_DEVCTL_NOSNOOP_EN): > > > > > > > > "Even when this bit is Set, a Function is only permitted to Set the No > > > > Snoop attribute on a transaction when it can guarantee that the > > > > address of the transaction is not stored in any cache in the system." > > > > > > > > I wouldn't think the function itself has such visibility and it would > > > > leave the problem of reestablishing coherency to the driver, but am I > > > > overlooking something that implicitly makes this safe? > > > > > > I think it is just bad spec language! People are clearly using > > > no-snoop on cachable memory today. The authors must have had some > > > other usage in mind than what the industry actually did. > > > > sure no-snoop can be used on cacheable memory but then the driver > > needs to flush the cache before triggering the no-snoop DMA so it > > still meets the spec "the address of the transaction is not stored > > in any cache in the system". > > Flush does not mean evict.. The way I read the above it is trying to > say the driver must map all the memory non-cachable to ensure it never > gets pulled into a cache in the first place. I think we should probably just fall back to your previous interpretation, it's bad spec language. It may not be possible to map the memory uncachable, it's a driver issue to sync the DMA as needed for coherency. > > > Maybe not entire, but as an additional step to reduce the cost of > > > this. ARM would like this for instance. > > > > I searched PCI_EXP_DEVCTL_NOSNOOP_EN but surprisingly it's not > > touched by i915 driver. sort of suggesting that Intel GPU doesn't follow > > the spec to honor that bit... > > Or the BIOS turns it on and the OS just leaves it.. This is kind of an unusual feature in that sense, the default value of PCI_EXP_DEVCTL_NOSNOOP_EN is enabled. It therefore might make sense that the i915 driver assumes that it can do no-snoop. The interesting case would be if it still does no-snoop if that bit were cleared prior to the driver binding or while the device is running. But I think this also means that regardless of virtualizing PCI_EXP_DEVCTL_NOSNOOP_EN, there will be momentary gaps around device resets where a device could legitimately perform no-snoop transactions. Thanks, Alex