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[142.68.80.239]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-454fda0d474sm43437701cf.0.2024.08.26.06.51.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2024 06:51:49 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.95) (envelope-from ) id 1sia8K-00BuxS-OT; Mon, 26 Aug 2024 10:51:48 -0300 Date: Mon, 26 Aug 2024 10:51:48 -0300 From: Jason Gunthorpe To: "Tian, Kevin" Cc: Baolu Lu , Vasant Hegde , "iommu@lists.linux.dev" , "joro@8bytes.org" , "will@kernel.org" , "robin.murphy@arm.com" , "suravee.suthikulpanit@amd.com" , "Liu, Yi L" Subject: Re: [PATCH 1/5] iommu: Enhance domain allocation code to take additional flags Message-ID: <20240826135148.GG3468552@ziepe.ca> References: <20240821133554.7405-1-vasant.hegde@amd.com> <20240821133554.7405-2-vasant.hegde@amd.com> <20240821163147.GZ3468552@ziepe.ca> <689eee1c-4b84-454b-8dc5-a5f35abe1631@linux.intel.com> <20240822124307.GC3468552@ziepe.ca> <7ca97716-fe84-426e-bc73-808f8182ddbf@linux.intel.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Mon, Aug 26, 2024 at 08:59:47AM +0000, Tian, Kevin wrote: > > First-stage has some limitations for an UNMANAGED domain. For example, If these are important then they need their own flags for iommufd to request them. > > - No separate controls for the Access/Dirty page tracking; > > You can do sw control upon whether to pre-set the a/d bit? The VMM can specify IOMMU_HWPT_ALLOC_NEST_PARENT | IOMMU_HWPT_ALLOC_DIRTY_TRACKING If this is important? > > - No Write-only permission support; > > What is the actual usage? What about a vIOMMU which > only supports stage-1? Is there some usage for this? > > - No page-level control for forcing snoop. > > again we don't have such page-granular snoop usage now and > in scalable mode we always set PGSNP field in the PASID entry > which makes the PTE snoop bit unused. Right no-snoop is expected to be domain global. > iirc arm smmu is using this policy too. Jason, is there any > similar limitations between stage-1 vs. stage-2 as above ? There are some difference, but more around performance. I think ARM would prefer to use the S2 in many cases because it may decrease the table depth by 1. AMD prefers to use their S2 for performance because it has more page size options. Jason