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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by BL6PEPF0001AB57.mail.protection.outlook.com (10.167.241.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Fri, 6 Sep 2024 12:13:48 +0000 Received: from purico-ed03host.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 6 Sep 2024 07:13:44 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v3 2/5] iommu/amd: Introduce helper functions to access and update 256-bit DTE Date: Fri, 6 Sep 2024 12:13:05 +0000 Message-ID: <20240906121308.5013-3-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240906121308.5013-1-suravee.suthikulpanit@amd.com> References: <20240906121308.5013-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB57:EE_|PH7PR12MB8038:EE_ X-MS-Office365-Filtering-Correlation-Id: 113e080e-5ae0-48d2-e55e-08dcce6d5cb8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Sep 2024 12:13:48.1364 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 113e080e-5ae0-48d2-e55e-08dcce6d5cb8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB57.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8038 The current implementation does not follow 128-bit write requirement to update DTE as specified in the AMD I/O Virtualization Techonology (IOMMU) Specification. Therefore, modify the struct dev_table_entry to contain union of u128 data array, and introduce two helper functions: * update_dte256() to update DTE using two 128-bit cmpxchg operations to update 256-bit DTE with the modified structure. * get_dte256() to copy 256-bit DTE to the provided structrue. In addition, when access/update 256-bit DTE, it needs to be locked to prevent cmpxchg128 failure and data tearing. Therefore, introduce a per-DTE spin_lock struct dev_data.dte_lock to provide synchronization across get_dte256() and update_dte256(). Suggested-by: Jason Gunthorpe Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu_types.h | 6 ++- drivers/iommu/amd/iommu.c | 80 +++++++++++++++++++++++++---- 2 files changed, 76 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index c9f9a598eb82..1836da2d9e60 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -833,6 +833,7 @@ struct devid_map { struct iommu_dev_data { /*Protect against attach/detach races */ spinlock_t lock; + spinlock_t dte_lock; /* DTE lock for 256-bit access */ struct list_head list; /* For domain->dev_list */ struct llist_node dev_data_list; /* For global dev_data_list */ @@ -883,7 +884,10 @@ extern struct amd_iommu *amd_iommus[MAX_IOMMUS]; * Structure defining one entry in the device table */ struct dev_table_entry { - u64 data[4]; + union { + u64 data[4]; + u128 data128[2]; + }; }; /* diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 87c5385ce3f2..b994e7837306 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -85,6 +85,45 @@ static void set_dte_entry(struct amd_iommu *iommu, * ****************************************************************************/ +static void update_dte256(struct amd_iommu *iommu, struct iommu_dev_data *dev_data, + struct dev_table_entry *new) +{ + struct dev_table_entry *dev_table = get_dev_table(iommu); + struct dev_table_entry *ptr = &dev_table[dev_data->devid]; + struct dev_table_entry old; + u128 tmp; + + lockdep_assert_held(&dev_data->dte_lock); + + old.data128[0] = ptr->data128[0]; + old.data128[1] = ptr->data128[1]; + + tmp = cmpxchg128(&ptr->data128[1], old.data128[1], new->data128[1]); + if (tmp == old.data128[1]) { + if (!try_cmpxchg128(&ptr->data128[0], &old.data128[0], new->data128[0])) { + /* Restore hi 128-bit */ + cmpxchg128(&ptr->data128[1], new->data128[1], tmp); + pr_err("%s: Failed. devid=%#x, dte=%016llx:%016llx:%016llx:%016llx\n", + __func__, dev_data->devid, new->data[0], new->data[1], + new->data[2], new->data[3]); + } + } +} + +static void get_dte256(struct amd_iommu *iommu, struct iommu_dev_data *dev_data, + struct dev_table_entry *dte) +{ + struct dev_table_entry *ptr; + struct dev_table_entry *dev_table = get_dev_table(iommu); + + lockdep_assert_held(&dev_data->dte_lock); + + ptr = &dev_table[dev_data->devid]; + + dte->data128[0] = ptr->data128[0]; + dte->data128[1] = ptr->data128[1]; +} + static inline bool pdom_is_v2_pgtbl_mode(struct protection_domain *pdom) { return (pdom && (pdom->pd_mode == PD_MODE_V2)); @@ -205,6 +244,7 @@ static struct iommu_dev_data *alloc_dev_data(struct amd_iommu *iommu, u16 devid) return NULL; spin_lock_init(&dev_data->lock); + spin_lock_init(&dev_data->dte_lock); dev_data->devid = devid; ratelimit_default_init(&dev_data->rs); @@ -232,9 +272,11 @@ static struct iommu_dev_data *search_dev_data(struct amd_iommu *iommu, u16 devid static int clone_alias(struct pci_dev *pdev, u16 alias, void *data) { + struct dev_table_entry dte; struct amd_iommu *iommu; - struct dev_table_entry *dev_table; + struct iommu_dev_data *dev_data, *alias_data; u16 devid = pci_dev_id(pdev); + int ret; if (devid == alias) return 0; @@ -243,13 +285,28 @@ static int clone_alias(struct pci_dev *pdev, u16 alias, void *data) if (!iommu) return 0; - amd_iommu_set_rlookup_table(iommu, alias); - dev_table = get_dev_table(iommu); - memcpy(dev_table[alias].data, - dev_table[devid].data, - sizeof(dev_table[alias].data)); + /* Get DTE for pdev */ + dev_data = dev_iommu_priv_get(&pdev->dev); + if (!dev_data) + return -EINVAL; - return 0; + spin_lock(&dev_data->dte_lock); + get_dte256(iommu, dev_data, &dte); + spin_unlock(&dev_data->dte_lock); + + /* Setup for alias */ + alias_data = search_dev_data(iommu, alias); + if (!alias_data) { + ret = -EINVAL; + goto out; + } + + spin_lock(&alias_data->dte_lock); + update_dte256(iommu, alias_data, &dte); + amd_iommu_set_rlookup_table(iommu, alias); + spin_unlock(&alias_data->dte_lock); +out: + return ret; } static void clone_aliases(struct amd_iommu *iommu, struct device *dev) @@ -583,10 +640,15 @@ static void amd_iommu_uninit_device(struct device *dev) static void dump_dte_entry(struct amd_iommu *iommu, u16 devid) { int i; - struct dev_table_entry *dev_table = get_dev_table(iommu); + struct dev_table_entry dte; + struct iommu_dev_data *dev_data = find_dev_data(iommu, devid); + + spin_lock(&dev_data->dte_lock); + get_dte256(iommu, dev_data, &dte); + spin_unlock(&dev_data->dte_lock); for (i = 0; i < 4; ++i) - pr_err("DTE[%d]: %016llx\n", i, dev_table[devid].data[i]); + pr_err("DTE[%d]: %016llx\n", i, dte.data[i]); } static void dump_command(unsigned long phys_addr) -- 2.34.1