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[142.68.128.5]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-45d92e30a82sm5511161cf.57.2024.10.03.06.27.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 06:27:25 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.95) (envelope-from ) id 1swLrZ-00ASSm-2s; Thu, 03 Oct 2024 10:27:25 -0300 Date: Thu, 3 Oct 2024 10:27:25 -0300 From: Jason Gunthorpe To: James Gowans Cc: linux-kernel@vger.kernel.org, Kevin Tian , Joerg Roedel , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Will Deacon , Robin Murphy , Mike Rapoport , "Madhavan T. Venkataraman" , iommu@lists.linux.dev, Sean Christopherson , Paolo Bonzini , kvm@vger.kernel.org, David Woodhouse , Lu Baolu , Alexander Graf , anthony.yznaga@oracle.com, steven.sistare@oracle.com, nh-open-source@amazon.com, "Saenz Julienne, Nicolas" Subject: Re: [RFC PATCH 03/13] iommu/intel: zap context table entries on kexec Message-ID: <20241003132725.GA2456194@ziepe.ca> References: <20240916113102.710522-1-jgowans@amazon.com> <20240916113102.710522-4-jgowans@amazon.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240916113102.710522-4-jgowans@amazon.com> On Mon, Sep 16, 2024 at 01:30:52PM +0200, James Gowans wrote: > Instead of fully shutting down the IOMMU on kexec, rather zap context > table entries for devices. This is the initial step to be able to > persist some domains. Once a struct iommu_domain can be marked > persistent then those persistent domains will be skipped when doing the > IOMMU shut down. > --- > drivers/iommu/intel/dmar.c | 1 + > drivers/iommu/intel/iommu.c | 34 ++++++++++++++++++++++++++++++---- > drivers/iommu/intel/iommu.h | 2 ++ > 3 files changed, 33 insertions(+), 4 deletions(-) We should probably try to avoid doing this kind of stuff in drivers. The core code can generically ask drivers to attach a BLOCKING domain as part of the kexec sequence and the core code can then decide which devices should be held over. There is also some complexity here around RMRs, we can't always apply a blocking domain... Not sure what you'd do in those cases. IIRC we already do something like this with the bus master enable on the PCI side?? At least, if the kernel is deciding to block DMA when the IOMMU is on it should do it consistently and inhibit the PCI device as well. Jason