From: "Aneesh Kumar K.V (Arm)" <aneesh.kumar@kernel.org>
To: linux-kernel@vger.kernel.org, iommu@lists.linux.dev
Cc: jean-philippe@linaro.org,
"Aneesh Kumar K.V (Arm)" <aneesh.kumar@kernel.org>,
Nicolin Chen <nicolinc@nvidia.com>,
Jason Gunthorpe <jgg@nvidia.com>, Will Deacon <will@kernel.org>
Subject: [PATCH] iommu/arm-smmu-v3: Fix overflow with sid_bits when computing level1 table index
Date: Tue, 8 Oct 2024 08:48:31 +0530 [thread overview]
Message-ID: <20241008031831.1254130-1-aneesh.kumar@kernel.org> (raw)
As per the spec, max bits of StreamID can be a value between 0 - 32
inclusive. With the FVP model, SMMU_IDR1.SID_SIZE returns value 32 which
results in arm_smmu_init_strtab_2lvl computing the last_sid_idx wrongly.
This caused a failure in ahci disk initialization with the FVP model as
shown below.
[ 7.147067] ata1.00: qc timeout after 5000 msecs (cmd 0xec)
[ 7.147177] ata1.00: failed to IDENTIFY (I/O error, err_mask=0x4)
[ 7.458320] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
[ 17.643140] ata1.00: qc timeout after 10000 msecs (cmd 0xec)
[ 17.643251] ata1.00: failed to IDENTIFY (I/O error, err_mask=0x4)
[ 17.643359] ata1: limiting SATA link speed to 3.0 Gbps
[ 17.954651] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 320)
[ 48.107079] ata1.00: qc timeout after 30000 msecs (cmd 0xec)
[ 48.107190] ata1.00: failed to IDENTIFY (I/O error, err_mask=0x4)
Cc: Nicolin Chen <nicolinc@nvidia.com>
Cc: Jason Gunthorpe <jgg@nvidia.com>
Cc: Will Deacon <will@kernel.org>
Fixes: ce410410f1a7 ("iommu/arm-smmu-v3: Add arm_smmu_strtab_l1/2_idx()")
Signed-off-by: Aneesh Kumar K.V (Arm) <aneesh.kumar@kernel.org>
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index 737c5b882355..01a2faee04bc 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -3625,7 +3625,7 @@ static int arm_smmu_init_strtab_2lvl(struct arm_smmu_device *smmu)
u32 l1size;
struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
unsigned int last_sid_idx =
- arm_smmu_strtab_l1_idx((1 << smmu->sid_bits) - 1);
+ arm_smmu_strtab_l1_idx((1UL << smmu->sid_bits) - 1);
/* Calculate the L1 size, capped to the SIDSIZE. */
cfg->l2.num_l1_ents = min(last_sid_idx + 1, STRTAB_MAX_L1_ENTRIES);
--
2.34.1
next reply other threads:[~2024-10-08 3:18 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-08 3:18 Aneesh Kumar K.V (Arm) [this message]
2024-10-08 4:11 ` [PATCH] iommu/arm-smmu-v3: Fix overflow with sid_bits when computing level1 table index Pranjal Shrivastava
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