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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH1PEPF0000A347.mail.protection.outlook.com (10.167.244.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8069.17 via Frontend Transport; Thu, 17 Oct 2024 14:02:08 +0000 Received: from kali.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 17 Oct 2024 09:02:02 -0500 From: Vasant Hegde To: , CC: , , , , , , , , Vasant Hegde Subject: [PATCH v3 00/12] iommu: Domain allocation enhancements Date: Thu, 17 Oct 2024 14:01:25 +0000 Message-ID: <20241017140137.6028-1-vasant.hegde@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A347:EE_|CY8PR12MB7635:EE_ X-MS-Office365-Filtering-Correlation-Id: 44ba578d-f6d2-46fb-ed9b-08dceeb44a77 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Oct 2024 14:02:08.9727 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 44ba578d-f6d2-46fb-ed9b-08dceeb44a77 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A347.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7635 This series adds iommu_paging_domain_alloc_flags() which takes flags to pass additional details for domain allocation (like domain with PASID support). Also adjusts core code to handler variuos domain allocations. Also updates AMD IOMMU driver domain allocation code. With this by default it will allocate domain with V2 page table for PASID capable device and v1 page table for rest of the devices. TODO: @Jason, @Kevin, @Baolu, With this series if driver implements domain_alloc_user() then we assume IOMMU always supports PASID. If IOMMU doesn't support PASID (ex: AMD driver not supporting V2 page table) and device is PASID capable, then driver will return error. Device probe will fail. I think if driver return error, core layer should retry without IOMMU_HWPT_ALLOC_PASID flag. Other option is indivisual driver in error path of domain_alloc_user allocating non-PASID capable domain. I prefer first option. Just wanted to discuss before implementing. Any preferred option here? OR any other better way to solve this? Note : vt-d specific changes is handled in separate series [1]. [1] https://lore.kernel.org/linux-iommu/20241011042722.73930-8-baolu.lu@linux.intel.com/ @Baolu, Do you want me to include above patch in this series so that it doesn't break intel driver? Thanks everyone who reviewed previous version and provided valuable feedbacks. This series is based on top of v6.12-rc3. This is also available at github : https://github.com/AMDESE/linux-iommu/tree/iommu_paging_domain_v3 Changes from V2 -> v3: - Added Review-by tags - Fixed warnings reported by 0-DAY CI - Added patch to enhance arm_smmu_domain_alloc_user() to support IOMMU_HWPT_ALLOC_PASID flag - Added new patch to check GIOSUP/GTSUP - Added patch to move V2 page table check to early_amd_iommu_init() - Added patch to adjust blocked/identity domain allocation in core layer - Dropped "iommu/amd: Add iommu_ops->domain_alloc_paging support" V2 : https://lore.kernel.org/linux-iommu/20240911101911.6269-1-vasant.hegde@amd.com/T/#t Changes from v1 -> v2: - Rebased on top of iommu/next - Split patches into smaller patches - Added global static identity domain support V1 : https://lore.kernel.org/linux-iommu/20240821133554.7405-1-vasant.hegde@amd.com/ RFC v2: https://lore.kernel.org/linux-iommu/fc8715e4-fb44-433b-a42a-7804118ebc57@amd.com/T/#t RFC v1 : https://lore.kernel.org/linux-iommu/7e249bc6-c578-40f0-aca7-835149a0ad39@amd.com/ Jason Gunthorpe (5): iommu: Refactor __iommu_domain_alloc() iommu: Introduce iommu_paging_domain_alloc_flags() iommu: Add new flag to explictly request PASID capable domain iommu: Put domain allocation in __iommu_group_alloc_blocking_domain() iommu: Create __iommu_alloc_identity_domain() Vasant Hegde (7): iommu/arm-smmu-v3: Enhance domain_alloc_user() to allocate PASID capable domain iommu/amd: Add helper function to check GIOSUP/GTSUP iommu/amd: Move V2 page table support check to early_amd_iommu_init() iommu/amd: Separate page table setup from domain allocation iommu/amd: Pass page table type as param to pdom_setup_pgtable() iommu/amd: Enhance amd_iommu_domain_alloc_user() iommu/amd: Implement global identity domain drivers/iommu/amd/amd_iommu.h | 8 +- drivers/iommu/amd/init.c | 18 ++- drivers/iommu/amd/iommu.c | 125 +++++++++----- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 3 + drivers/iommu/iommu.c | 171 +++++++++++++------- include/linux/iommu.h | 14 +- include/uapi/linux/iommufd.h | 6 + 7 files changed, 240 insertions(+), 105 deletions(-) -- 2.31.1