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Tue, 21 Jan 2025 03:29:14 -0800 (PST) Received: from tiger.hygon.cn ([112.64.138.194]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21c2cea1fdesm75385965ad.26.2025.01.21.03.29.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jan 2025 03:29:12 -0800 (PST) From: Wencheng Yang To: east.moutain.yang@gmail.com, alex.williamson@redhat.com, jgg@ziepe.ca Cc: iommu@lists.linux.dev, joro@8bytes.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, robin.murphy@arm.com, suravee.suthikulpanit@amd.com, will@kernel.org Subject: [PATCH v3 3/3] iommu/amd:Clear encryption bit if the mapping is for device MMIO Date: Tue, 21 Jan 2025 19:28:36 +0800 Message-ID: <20250121112836.525046-3-east.moutain.yang@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250121112836.525046-1-east.moutain.yang@gmail.com> References: <20250121112836.525046-1-east.moutain.yang@gmail.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit When SME is enabled, memory encryption bit is set in IOMMU page table pte entry, it works fine if the pfn of the pte entry is memory. However, if the pfn is MMIO address, for example, map other device's mmio space to its io page table, in such situation, setting memory encryption bit in pte would cause P2P failure. Clear memory encryption bit in io page table if the mapping is MMIO rather than memory. Signed-off-by: Wencheng Yang --- drivers/iommu/amd/amd_iommu_types.h | 7 ++++--- drivers/iommu/amd/io_pgtable.c | 2 ++ drivers/iommu/amd/io_pgtable_v2.c | 5 ++++- drivers/iommu/amd/iommu.c | 2 ++ 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index fdb0357e0bb9..b0f055200cf3 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -434,9 +434,10 @@ #define IOMMU_PTE_PAGE(pte) (iommu_phys_to_virt((pte) & IOMMU_PAGE_MASK)) #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07) -#define IOMMU_PROT_MASK 0x03 -#define IOMMU_PROT_IR 0x01 -#define IOMMU_PROT_IW 0x02 +#define IOMMU_PROT_MASK 0x07 +#define IOMMU_PROT_IR 0x01 +#define IOMMU_PROT_IW 0x02 +#define IOMMU_PROT_MMIO 0x04 #define IOMMU_UNITY_MAP_FLAG_EXCL_RANGE (1 << 2) diff --git a/drivers/iommu/amd/io_pgtable.c b/drivers/iommu/amd/io_pgtable.c index f3399087859f..dff887958a56 100644 --- a/drivers/iommu/amd/io_pgtable.c +++ b/drivers/iommu/amd/io_pgtable.c @@ -373,6 +373,8 @@ static int iommu_v1_map_pages(struct io_pgtable_ops *ops, unsigned long iova, __pte |= IOMMU_PTE_IR; if (prot & IOMMU_PROT_IW) __pte |= IOMMU_PTE_IW; + if (prot & IOMMU_PROT_MMIO) + __pte = __sme_clr(__pte); for (i = 0; i < count; ++i) pte[i] = __pte; diff --git a/drivers/iommu/amd/io_pgtable_v2.c b/drivers/iommu/amd/io_pgtable_v2.c index c616de2c5926..55f969727dea 100644 --- a/drivers/iommu/amd/io_pgtable_v2.c +++ b/drivers/iommu/amd/io_pgtable_v2.c @@ -65,7 +65,10 @@ static u64 set_pte_attr(u64 paddr, u64 pg_size, int prot) { u64 pte; - pte = __sme_set(paddr & PM_ADDR_MASK); + pte = paddr & PM_ADDR_MASK; + if (!(prot & IOMMU_PROT_MMIO)) + pte = __sme_set(pte); + pte |= IOMMU_PAGE_PRESENT | IOMMU_PAGE_USER; pte |= IOMMU_PAGE_ACCESS | IOMMU_PAGE_DIRTY; diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 16f40b8000d7..9194ad681504 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2578,6 +2578,8 @@ static int amd_iommu_map_pages(struct iommu_domain *dom, unsigned long iova, prot |= IOMMU_PROT_IR; if (iommu_prot & IOMMU_WRITE) prot |= IOMMU_PROT_IW; + if (iommu_prot & IOMMU_MMIO) + prot |= IOMMU_PROT_MMIO; if (ops->map_pages) { ret = ops->map_pages(ops, iova, paddr, pgsize, -- 2.43.0