From: Sean Christopherson <seanjc@google.com>
To: Joerg Roedel <joro@8bytes.org>
Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org,
Sean Christopherson <seanjc@google.com>
Subject: [PATCH] iommu/amd: Fix a stale comment about which legacy mode is user visible
Date: Fri, 14 Mar 2025 20:21:48 -0700 [thread overview]
Message-ID: <20250315032148.2377902-1-seanjc@google.com> (raw)
Update a stale comment about which of the legacy modes is visible to the
user, i.e. can be forced via amd_iommu_intr=legacy.
Fixes: b74aa02d7a30 ("iommu/amd: Fix legacy interrupt remapping for x2APIC-enabled system")
Signed-off-by: Sean Christopherson <seanjc@google.com>
---
drivers/iommu/amd/amd_iommu_types.h | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index 23caea22f8dc..f7877abd0091 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -968,12 +968,13 @@ static inline int get_hpet_devid(int id)
}
enum amd_iommu_intr_mode_type {
+ /*
+ * The legacy format mode is not visible to users to prevent the user
+ * from crashing x2APIC systems, which for all intents and purposes
+ * require 128-bit IRTEs. The legacy format will be forced as needed
+ * when hardware doesn't support 128-bit IRTEs.
+ */
AMD_IOMMU_GUEST_IR_LEGACY,
-
- /* This mode is not visible to users. It is used when
- * we cannot fully enable vAPIC and fallback to only support
- * legacy interrupt remapping via 128-bit IRTE.
- */
AMD_IOMMU_GUEST_IR_LEGACY_GA,
AMD_IOMMU_GUEST_IR_VAPIC,
};
base-commit: ea9bd29a9c0d757b3384ae3e633e6bbaddf00725
--
2.49.0.rc1.451.g8f38331e32-goog
next reply other threads:[~2025-03-15 3:21 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-15 3:21 Sean Christopherson [this message]
2026-04-06 23:03 ` [PATCH] iommu/amd: Fix a stale comment about which legacy mode is user visible Sean Christopherson
2026-04-07 14:47 ` Wei Wang
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