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[142.167.219.86]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7c7a8a0de1esm1088777885a.103.2025.04.16.11.17.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Apr 2025 11:17:59 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1u57Kh-00000004wJB-0tjv; Wed, 16 Apr 2025 15:17:59 -0300 Date: Wed, 16 Apr 2025 15:17:59 -0300 From: Jason Gunthorpe To: Jacob Pan Cc: Shyam Saini , iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, virtualization@lists.linux.dev, will@kernel.org, eric.auger@redhat.com, code@tyhicks.com, eahariha@linux.microsoft.com, vijayb@linux.microsoft.com Subject: Re: [PATCH v2 0/3] arm-smmu: select suitable IOVA Message-ID: <20250416181759.GF493866@ziepe.ca> References: <20250410225030.2528385-1-shyamsaini@linux.microsoft.com> <20250410230008.GA6905@ziepe.ca> <67fff12d.650a0220.208c7c.d69dSMTPIN_ADDED_BROKEN@mx.google.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <67fff12d.650a0220.208c7c.d69dSMTPIN_ADDED_BROKEN@mx.google.com> On Wed, Apr 16, 2025 at 11:04:27AM -0700, Jacob Pan wrote: > Per last discussion "SMMU driver have a list of potential addresses and > select the first one that does not intersect with the non-working IOVA > ranges.". If we don't know what the "non-working IOVA" is, how do we > know it does not intersect the "potential addresses"? I had understood from previous discussions that this platform is properly creating IOMMU_RESV_RESERVED regions for the IOVA that doesn't work. Otherwise everything is broken.. Presumably that happens through iommu_dma_get_resv_regions() calling of_iommu_get_resv_regions() on a DT platform. There is a schema describing how to do this, so platform firmware should be able to do it.. So the fix seems trivial enough to me: diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index b4c21aaed1266a..ebba18579151bc 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3562,17 +3562,29 @@ static int arm_smmu_of_xlate(struct device *dev, static void arm_smmu_get_resv_regions(struct device *dev, struct list_head *head) { - struct iommu_resv_region *region; - int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; - - region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, - prot, IOMMU_RESV_SW_MSI, GFP_KERNEL); - if (!region) - return; - - list_add_tail(®ion->list, head); + static const u64 msi_bases[] = { MSI_IOVA_BASE, 0x12340000 }; iommu_dma_get_resv_regions(dev, head); + + /* + * Use the first msi_base that does not intersect with a platform + * reserved region. The SW MSI base selection is entirely arbitary. + */ + for (i = 0; i != ARRAY_SIZE(msi_bases); i++) { + struct iommu_resv_region *region; + + if (resv_intersects(msi_bases[i], MSI_IOVA_LENGTH)) + continue; + + region = iommu_alloc_resv_region(msi_bases[i], MSI_IOVA_LENGTH, + IOMMU_WRITE | IOMMU_NOEXEC | + IOMMU_MMIO, + IOMMU_RESV_SW_MSI, GFP_KERNEL); + if (!region) + return; + list_add_tail(®ion->list, head); + return; + } } static int arm_smmu_dev_enable_feature(struct device *dev, Jason