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[142.167.56.70]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4a72a4b0e93sm65849681cf.42.2025.06.17.12.57.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jun 2025 12:57:21 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1uRcQq-00000006ckX-2tam; Tue, 17 Jun 2025 16:57:20 -0300 Date: Tue, 17 Jun 2025 16:57:20 -0300 From: Jason Gunthorpe To: "Michael S. Tsirkin" Cc: Demi Marie Obenour , Jason Wang , Xuan Zhuo , Eugenio =?utf-8?B?UMOpcmV6?= , "Rafael J. Wysocki" , Len Brown , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Joerg Roedel , Will Deacon , Robin Murphy , Alyssa Ross , virtualization@lists.linux.dev, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, iommu@lists.linux.dev, x86@kernel.org, Spectrum OS Development Subject: Re: Virtio-IOMMU interrupt remapping design Message-ID: <20250617195720.GI1376515@ziepe.ca> References: <> <20250616132031.GB1354058@ziepe.ca> <20250617154331-mutt-send-email-mst@kernel.org> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250617154331-mutt-send-email-mst@kernel.org> On Tue, Jun 17, 2025 at 03:44:20PM -0400, Michael S. Tsirkin wrote: > On Mon, Jun 16, 2025 at 10:20:31AM -0300, Jason Gunthorpe wrote: > > On Sun, Jun 15, 2025 at 02:47:15PM -0400, Demi Marie Obenour wrote: > > > > > Is a paravirtualized IOMMU with interrupt remapping something that makes > > > sense? > > > > IMHO linking interrupt remapping to the iommu is a poor design, > > interrupt routing belongs in the irq subsystem, not in the iommu. > > > > The fact AMD and Intel both coupled their interrupt routing to their > > iommu hardware is just a weird design decision. ARM didn't do this, > > for instance. > > why does it matter in which device it resides? It would cleanup the boot process if the IRQ components were available at the same time as the IRQ drivers instead of much later when the iommu gets plugged in. > Way I see it, there is little reason to remap interrupts without > also using an iommu, so why not a single device. what did I miss? Remapping interrupts can be understood to be virtualizing the MSI addr/data pair space so that the CPU controls where the interrupt goes though its internal tables not the device through the addr/data. On x86 you also need to use remapping to exceed the max CPU count that can be encoded in the MSI, no iommu required to need this. There is also some stuff related to IMS that could get improved here. You don't need an iommu to enjoy those benefits. Jason