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Mon, 18 Aug 2025 08:53:12 -0700 (PDT) Received: from ziepe.ca ([130.41.10.202]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70ba90bcf7esm54232646d6.31.2025.08.18.08.53.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Aug 2025 08:53:11 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1uo2AY-00000004OfV-46ks; Mon, 18 Aug 2025 12:53:10 -0300 Date: Mon, 18 Aug 2025 12:53:10 -0300 From: Jason Gunthorpe To: Shyam Saini Cc: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, virtualization@lists.linux.dev, will@kernel.org, jacob.pan@linux.microsoft.com, eric.auger@redhat.com, code@tyhicks.com, eahariha@linux.microsoft.com, vijayb@linux.microsoft.com, bboscaccy@linux.microsoft.com, robh@kernel.org, saravanak@google.com, krzk+dt@kernel.org, conor+dt@kernel.org, lizhi.hou@amd.com, clement.leger@bootlin.com Subject: Re: [PATCH v3 2/3] iommu/of: fix device tree configuration for PCI devices Message-ID: <20250818155310.GG599331@ziepe.ca> References: <20250806215539.1240561-1-shyamsaini@linux.microsoft.com> <20250806215539.1240561-3-shyamsaini@linux.microsoft.com> <20250808121515.GE377696@ziepe.ca> <20250814233018.GA31418@linuxonhyperv3.guj3yctzbm1etfxqx2vob5hsef.xx.internal.cloudapp.net> <20250815003958.GE599331@ziepe.ca> <20250815023236.GA30997@linuxonhyperv3.guj3yctzbm1etfxqx2vob5hsef.xx.internal.cloudapp.net> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250815023236.GA30997@linuxonhyperv3.guj3yctzbm1etfxqx2vob5hsef.xx.internal.cloudapp.net> On Thu, Aug 14, 2025 at 07:32:36PM -0700, Shyam Saini wrote: > On Thu, Aug 14, 2025 at 09:39:58PM -0300, Jason Gunthorpe wrote: > > On Thu, Aug 14, 2025 at 04:30:18PM -0700, Shyam Saini wrote: > > > or were you referring to [2]? > > > > > > In that case, the PCI child node data needs to be parsed, which is > > > currently handled individually by each host controller driver. > > > > Yes, this looks like it may be what I was thinking of, the pci@1,0 > > specifes the BDF effectively > > In that case, we'll need to parse the child DTS nodes properly > within of_iommu_get_resv_regions(). I'll include this in v4. Kinda surprised this isn't happening already? It would be good to refer to the original specs and describe how whatetever you propose is aligned there. > > Presumably this is a fixed issue of the platform. You never did > > explain how your system has such werdio behavior, or how something > > like iommu=pt can function on it... > Yes, this issue is platform-specific. On this platform, the default MSI IOVA > range overlaps with an address region that is reserved for another purpose, > Other than that we haven't observed any obvious issues for DMA operations Usually DRAM is at the default MSI IOVA address, so if you run iommu=pt then presumably your DRAM map has a nice hole in it.. But maybe the memory map told the OS about that. Jason