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AJvYcCX1YxhjEfkK98JWG4FUa/emo+wGgedO7WVpKFgh2jRWL2VlmGFg5XQ9xvrjKXpP8wTgUW3hrw==@lists.linux.dev X-Gm-Message-State: AOJu0Yx7m5ei95GTvwjKHTahdrS23TkTY9zHhEvDW7j74/pkm0rSE8VN TG3PHvpLlMbhlF1IUj+2/KaAj2NMJfRczMGvFNAemLqpL/+U1+7Vu218erYYG1H2EgVTTmrO8gK ulcXoENe0esnoEg== X-Google-Smtp-Source: AGHT+IEhkGtNHGU6UMmeB0BAIZ4sLir5Qlb/i2T9JqWqyDJv4XQTeVZhQ/vtD+ljWCO9zlGmXGV9Ovms10Lr6A== X-Received: from wmbhc5.prod.google.com ([2002:a05:600c:8705:b0:458:6799:d779]) (user=smostafa job=prod-delivery.src-stubby-dispatcher) by 2002:a05:600c:3b05:b0:43d:745a:5a50 with SMTP id 5b1f17b1804b1-45b479ea5a9mr2802145e9.19.1755640359305; Tue, 19 Aug 2025 14:52:39 -0700 (PDT) Date: Tue, 19 Aug 2025 21:51:44 +0000 In-Reply-To: <20250819215156.2494305-1-smostafa@google.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250819215156.2494305-1-smostafa@google.com> X-Mailer: git-send-email 2.51.0.rc1.167.g924127e9c0-goog Message-ID: <20250819215156.2494305-17-smostafa@google.com> Subject: [PATCH v4 16/28] iommu/arm-smmu-v3-kvm: Create array for hyp SMMUv3 From: Mostafa Saleh To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev Cc: maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, robin.murphy@arm.com, jean-philippe@linaro.org, qperret@google.com, tabba@google.com, jgg@ziepe.ca, mark.rutland@arm.com, praan@google.com, Mostafa Saleh Content-Type: text/plain; charset="UTF-8" As the hypervisor has no access to firmware tables, the device discovery is done from the kernel, where it parses firmware tables and populates a list of devices to the hypervisor, which later takes over. At the moment only the device tree is supported. Signed-off-by: Mostafa Saleh --- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-kvm.c | 93 ++++++++++++++++++- .../iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h | 13 +++ 2 files changed, 105 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kvm.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kvm.c index ac4eac6d567f..27ea39c0fb1f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kvm.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kvm.c @@ -7,6 +7,7 @@ #include #include +#include #include #include "arm-smmu-v3.h" @@ -14,6 +15,75 @@ extern struct kvm_iommu_ops kvm_nvhe_sym(smmu_ops); +static size_t kvm_arm_smmu_count; +static struct hyp_arm_smmu_v3_device *kvm_arm_smmu_array; + +static void kvm_arm_smmu_array_free(void) +{ + int order; + + order = get_order(kvm_arm_smmu_count * sizeof(*kvm_arm_smmu_array)); + free_pages((unsigned long)kvm_arm_smmu_array, order); +} + +/* + * The hypervisor have to know the basic information about the SMMUs + * from the firmware. + * This has to be done before the SMMUv3 probes and does anything meaningful + * with the hardware, otherwise it becomes harder to reason about the SMMU + * state and we'd require to hand-off the state to the hypervisor at certain point + * while devices are live, which is complicated and dangerous. + * Instead, the hypervisor is interested in a very small part of the probe path, + * so just add a separate logic for it. + */ +static int kvm_arm_smmu_array_alloc(void) +{ + int smmu_order; + struct device_node *np; + int ret; + int i = 0; + + kvm_arm_smmu_count = 0; + for_each_compatible_node(np, NULL, "arm,smmu-v3") + kvm_arm_smmu_count++; + + if (!kvm_arm_smmu_count) + return -ENODEV; + + smmu_order = get_order(kvm_arm_smmu_count * sizeof(*kvm_arm_smmu_array)); + kvm_arm_smmu_array = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, smmu_order); + if (!kvm_arm_smmu_array) + return -ENOMEM; + + /* Basic device tree parsing. */ + for_each_compatible_node(np, NULL, "arm,smmu-v3") { + struct resource res; + + ret = of_address_to_resource(np, 0, &res); + if (ret) + goto out_err; + kvm_arm_smmu_array[i].mmio_addr = res.start; + kvm_arm_smmu_array[i].mmio_size = resource_size(&res); + if (kvm_arm_smmu_array[i].mmio_size < SZ_128K) { + pr_err("SMMUv3(%s) has unsupported size(0x%lx)\n", np->name, + kvm_arm_smmu_array[i].mmio_size); + ret = -EINVAL; + goto out_err; + } + + if (of_dma_is_coherent(np)) + kvm_arm_smmu_array[i].features |= ARM_SMMU_FEAT_COHERENCY; + + i++; + } + + return 0; + +out_err: + kvm_arm_smmu_array_free(); + return ret; +} + size_t smmu_hyp_pgt_pages(void) { /* @@ -27,10 +97,31 @@ size_t smmu_hyp_pgt_pages(void) static int kvm_arm_smmu_v3_register(void) { + int ret; + if (!is_protected_kvm_enabled()) return 0; - return kvm_iommu_register_driver(kern_hyp_va(lm_alias(&kvm_nvhe_sym(smmu_ops)))); + ret = kvm_arm_smmu_array_alloc(); + if (ret) + return ret; + + ret = kvm_iommu_register_driver(kern_hyp_va(lm_alias(&kvm_nvhe_sym(smmu_ops)))); + if (ret) + goto out_err; + + /* + * These variables are stored in the nVHE image, and won't be accessible + * after KVM initialization. Ownership of kvm_arm_smmu_array will be + * transferred to the hypervisor as well. + */ + kvm_hyp_arm_smmu_v3_smmus = kvm_arm_smmu_array; + kvm_hyp_arm_smmu_v3_count = kvm_arm_smmu_count; + return ret; + +out_err: + kvm_arm_smmu_array_free(); + return ret; }; core_initcall(kvm_arm_smmu_v3_register); diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h index f6ad91d3fb85..744ee2b7f0b4 100644 --- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h @@ -4,7 +4,20 @@ #include +/* + * Parameters from the trusted host: + * @mmio_addr base address of the SMMU registers + * @mmio_size size of the registers resource + * @features Features of SMMUv3, subset of the main driver + * + * Other members are filled and used at runtime by the SMMU driver. + * @base Virtual address of SMMU registers + */ struct hyp_arm_smmu_v3_device { + phys_addr_t mmio_addr; + size_t mmio_size; + void __iomem *base; + u32 features; }; extern size_t kvm_nvhe_sym(kvm_hyp_arm_smmu_v3_count); -- 2.51.0.rc1.167.g924127e9c0-goog