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(unknown [IPv6:2a01:e0a:120:3210:f39:d9a9:8ef1:f69a]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: benjamin.gaignard) by bali.collaboradmins.com (Postfix) with ESMTPSA id 53CE817E0963; Mon, 25 Aug 2025 17:34:58 +0200 (CEST) From: Benjamin Gaignard To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de, nicolas.dufresne@collabora.com, jgg@ziepe.ca, p.zabel@pengutronix.de, mchehab@kernel.org Cc: iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, kernel@collabora.com, linux-media@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v7 4/6] media: verisilicon: AV1: Restore IOMMU context before decoding a frame Date: Mon, 25 Aug 2025 17:34:43 +0200 Message-ID: <20250825153450.150071-5-benjamin.gaignard@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250825153450.150071-1-benjamin.gaignard@collabora.com> References: <20250825153450.150071-1-benjamin.gaignard@collabora.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit AV1 is a stateless decoder and multiple AV1 bitstreams could be decoded at the same time. Each decoding context got it own iommu domain which need to be restored before each frame. To be sure that iommu context is correctly set AV1 driver detach and attach before decoding the frame. Signed-off-by: Benjamin Gaignard --- changes in version 7: - add a patch in AV1 video decoder to manage per context iommu domain. drivers/media/platform/verisilicon/hantro.h | 5 +++++ drivers/media/platform/verisilicon/hantro_drv.c | 11 +++++++++++ .../platform/verisilicon/rockchip_vpu981_hw_av1_dec.c | 10 ++++++++++ 3 files changed, 26 insertions(+) diff --git a/drivers/media/platform/verisilicon/hantro.h b/drivers/media/platform/verisilicon/hantro.h index 81328c63b796..a28a181013b9 100644 --- a/drivers/media/platform/verisilicon/hantro.h +++ b/drivers/media/platform/verisilicon/hantro.h @@ -12,6 +12,9 @@ #ifndef HANTRO_H_ #define HANTRO_H_ +#include +#include +#include #include #include #include @@ -266,6 +269,8 @@ struct hantro_ctx { struct hantro_postproc_ctx postproc; bool need_postproc; + struct iommu_domain *iommu_domain; + /* Specific for particular codec modes. */ union { struct hantro_h264_dec_hw_ctx h264_dec; diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c index 8542238e0fb1..feec8e6fb504 100644 --- a/drivers/media/platform/verisilicon/hantro_drv.c +++ b/drivers/media/platform/verisilicon/hantro_drv.c @@ -675,6 +675,13 @@ static int hantro_open(struct file *filp) } ctx->fh.ctrl_handler = &ctx->ctrl_handler; + if (use_dma_iommu(ctx->dev->v4l2_dev.dev)) { + ctx->iommu_domain = iommu_paging_domain_alloc(ctx->dev->v4l2_dev.dev); + + if (!ctx->iommu_domain) + vpu_err("cannot alloc new empty domain\n"); + } + return 0; err_fh_free: @@ -698,6 +705,10 @@ static int hantro_release(struct file *filp) v4l2_fh_del(&ctx->fh); v4l2_fh_exit(&ctx->fh); v4l2_ctrl_handler_free(&ctx->ctrl_handler); + + if (ctx->iommu_domain) + iommu_domain_free(ctx->iommu_domain); + kfree(ctx); return 0; diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c index e4703bb6be7c..b3e52387234f 100644 --- a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c +++ b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c @@ -2095,12 +2095,22 @@ rockchip_vpu981_av1_dec_set_output_buffer(struct hantro_ctx *ctx) hantro_write_addr(vpu, AV1_TILE_OUT_MV, mv_addr); } +static void rockchip_vpu981_av1_restore_iommu(struct hantro_ctx *ctx) +{ + if (ctx->iommu_domain) { + iommu_attach_device(ctx->iommu_domain, ctx->dev->v4l2_dev.dev); + iommu_detach_device(ctx->iommu_domain, ctx->dev->v4l2_dev.dev); + } +} + int rockchip_vpu981_av1_dec_run(struct hantro_ctx *ctx) { struct hantro_dev *vpu = ctx->dev; struct vb2_v4l2_buffer *vb2_src; int ret; + rockchip_vpu981_av1_restore_iommu(ctx); + hantro_start_prepare_run(ctx); ret = rockchip_vpu981_av1_dec_prepare_run(ctx); -- 2.43.0