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Thu, 18 Sep 2025 15:43:24 -0700 (PDT) Received: from ziepe.ca ([130.41.10.202]) by smtp.gmail.com with ESMTPSA id 5614622812f47-43d5c85d269sm1274466b6e.23.2025.09.18.15.43.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Sep 2025 15:43:23 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1uzNLW-000000091yf-0M6j; Thu, 18 Sep 2025 19:43:22 -0300 Date: Thu, 18 Sep 2025 19:43:22 -0300 From: Jason Gunthorpe To: Will Deacon Cc: Shyam Saini , thierry.reding@gmail.com, robin.murphy@arm.com, robh@kernel.org, joro@8bytes.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, virtualization@lists.linux.dev, jacob.pan@linux.microsoft.com, eric.auger@redhat.com, code@tyhicks.com, eahariha@linux.microsoft.com, vijayb@linux.microsoft.com, bboscaccy@linux.microsoft.com, saravanak@google.com, krzk+dt@kernel.org, conor+dt@kernel.org, lizhi.hou@amd.com, clement.leger@bootlin.com Subject: Re: [PATCH v4 3/4] arm-smmu: select suitable MSI IOVA Message-ID: <20250918224322.GR1326709@ziepe.ca> References: <20250909154600.910110-1-shyamsaini@linux.microsoft.com> <20250909154600.910110-4-shyamsaini@linux.microsoft.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Thu, Sep 18, 2025 at 05:49:39PM +0100, Will Deacon wrote: > Given that we're walking over the reserved regions to see if we have a > collision with MSI_IOVA_BASE, why not allocate the base address > dynamically if we detect a collision rather than having yet another > hard-coded address which we can't guarantee won't be problematic in future? I'm nervous about this. Right now the MSI_IOVA is actually UAPI and things like VFIO/qmeu need to accomodate it's placement in their own memory maps. Nicolin has some patches on the iommufd side to let userspace select the MSI address instead, but they are not done yet. So, randomly picking an address sounds like a bad idea to me, it would almost certainly unpredictably break qemu.. Hopefully by the time we need a 3rd one we have the userspace MSI control and then we could make reasonably make the kernel automatically select. Jason