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Sat, 20 Sep 2025 13:39:05 -0700 (PDT) Received: from localhost ([140.82.166.162]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-53d3a590fcfsm3682210173.11.2025.09.20.13.39.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Sep 2025 13:39:05 -0700 (PDT) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: jgg@nvidia.com, zong.li@sifive.com, tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atish.patra@linux.dev, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, alex@ghiti.fr Subject: [RFC PATCH v2 10/18] RISC-V: Define irqbypass vcpu_info Date: Sat, 20 Sep 2025 15:39:00 -0500 Message-ID: <20250920203851.2205115-30-ajones@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250920203851.2205115-20-ajones@ventanamicro.com> References: <20250920203851.2205115-20-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The vcpu_info parameter to irq_set_vcpu_affinity() effectively defines an arch specific IOMMU <=> hypervisor protocol. Provide a definition for the RISCV IOMMU. Signed-off-by: Andrew Jones --- arch/riscv/include/asm/irq.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index 59c975f750c9..27ff169d1b77 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -25,6 +25,15 @@ struct fwnode_handle *riscv_get_intc_hwnode(void); int riscv_get_hart_index(struct fwnode_handle *fwnode, u32 logical_index, u32 *hart_index); +struct riscv_iommu_ir_vcpu_info { + u64 gpa; + u64 hpa; + u64 msi_addr_mask; + u64 msi_addr_pattern; + u32 group_index_bits; + u32 group_index_shift; +}; + #ifdef CONFIG_ACPI enum riscv_irqchip_type { -- 2.49.0