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[47.55.120.4]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-882862d0944sm115395396d6.9.2025.11.18.06.30.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Nov 2025 06:30:04 -0800 (PST) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1vLMiZ-00000000NFZ-1yj6; Tue, 18 Nov 2025 10:30:03 -0400 Date: Tue, 18 Nov 2025 10:30:03 -0400 From: Jason Gunthorpe To: Ankit Agrawal Cc: Leon Romanovsky , Bjorn Helgaas , Logan Gunthorpe , Jens Axboe , Robin Murphy , Joerg Roedel , Will Deacon , Marek Szyprowski , Andrew Morton , Jonathan Corbet , Sumit Semwal , Christian =?utf-8?B?S8O2bmln?= , Kees Cook , "Gustavo A. R. Silva" , Yishai Hadas , Shameer Kolothum , Kevin Tian , Alex Williamson , Krishnakant Jaju , Matt Ochs , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-block@vger.kernel.org" , "iommu@lists.linux.dev" , "linux-mm@kvack.org" , "linux-doc@vger.kernel.org" , "linux-media@vger.kernel.org" , "dri-devel@lists.freedesktop.org" , "linaro-mm-sig@lists.linaro.org" , "kvm@vger.kernel.org" , "linux-hardening@vger.kernel.org" , Alex Mastro , Nicolin Chen Subject: Re: [PATCH v8 11/11] vfio/nvgrace: Support get_dmabuf_phys Message-ID: <20251118143003.GH17968@ziepe.ca> References: <20251111-dmabuf-vfio-v8-0-fd9aa5df478f@nvidia.com> <20251111-dmabuf-vfio-v8-11-fd9aa5df478f@nvidia.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Tue, Nov 18, 2025 at 07:59:20AM +0000, Ankit Agrawal wrote: > +       if (nvdev->resmem.memlength && region_index == RESMEM_REGION_INDEX) { > +               /* > +                * The P2P properties of the non-BAR memory is the same as the > +                * BAR memory, so just use the provider for index 0. Someday > +                * when CXL gets P2P support we could create CXLish providers > +                * for the non-BAR memory. > +                */ > +               mem_region = &nvdev->resmem; > +       } else if (region_index == USEMEM_REGION_INDEX) { > +               /* > +                * This is actually cachable memory and isn't treated as P2P in > +                * the chip. For now we have no way to push cachable memory > +                * through everything and the Grace HW doesn't care what caching > +                * attribute is programmed into the SMMU. So use BAR 0. > +                */ > +               mem_region = &nvdev->usemem; > +       } > + > > Can we replace this with nvgrace_gpu_memregion()? Yes, looks like But we need to preserve the comments above as well somehow. Jason