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[47.55.120.4]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8846e54c9d0sm47151386d6.26.2025.11.21.15.35.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Nov 2025 15:35:46 -0800 (PST) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1vMafJ-00000001bdi-3fWH; Fri, 21 Nov 2025 19:35:45 -0400 Date: Fri, 21 Nov 2025 19:35:45 -0400 From: Jason Gunthorpe To: Sairaj Kodilkar Cc: joro@8bytes.org, suravee.suthikulpanit@amd.com, will@kernel.org, robin.murphy@arm.com, kevin.tian@intel.com, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, vasant.hegde@amd.com Subject: Re: [RFC PATCH] iommu/amd: Add control register in `struct iommu_hw_info_amd` Message-ID: <20251121233545.GJ233636@ziepe.ca> References: <20251029095846.4486-1-sarunkod@amd.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251029095846.4486-1-sarunkod@amd.com> On Wed, Oct 29, 2025 at 03:28:46PM +0530, Sairaj Kodilkar wrote: > When user does IOMMU_GET_HW_INFO ioctl, read the IOMMU control > register (MMIO offset 0x0018) and return it as part of > `struct iommu_hw_info_amd`. > > Userspace can use this information to determine the features > supported by the underlying host kernel. > > Signed-off-by: Sairaj Kodilkar > --- > > The patch exposes the control register to the user space so that QEMU > can determine the list of features enabled by the host IOMMU driver > when there are passthrough devices. QEMU can use this information to > selectively enable the guest feature. One example of such feature is > enabling upto 2048 MSIs for passthrough devices. QEMU must not enable > this feature for passthrough devices when host IOMMU driver has not > enabled it. Please document in the uapi header what bits are meaningful and userspace can safely access.. You are OK that a 0 register means the kernel is old? Jason