Re: [PATCH v2 0/3] iommu/vt-d: Ensure atomicity in context and PASID entry updates

Jason Gunthorpe
2026-01-20T13:56:58Z

On Tue, Jan 20, 2026 at 02:18:11PM +0800, Lu Baolu wrote:
> This is a follow-up from recent discussions in the iommu community
> mailing list [1] [2] regarding potential race conditions in table
> entry updates.
>
> The Intel VT-d hardware fetches translation table entries (context
> entries and PASID entries) in 128-bit (16-byte) chunks. Currently, the
> Linux driver often updates these entries using multiple 64-bit writes.
> This creates a race condition where the IOMMU hardware may fetch a
> "torn" entry — a mixture of old and new data — during a CPU update. This
> can lead to unpredictable hardware behavior, spurious faults, or system
> instability.
>
> This addresses these atomicity issues by following the translation table
> entry ownership handshake protocal recommended by the VT-d specification.

This seems like a reasonable first series

Thanks,
Jason