From: Lu Baolu <baolu.lu@linux.intel.com>
To: Joerg Roedel <joro@8bytes.org>
Cc: Yi Liu <yi.l.liu@intel.com>, Dmytro Maluka <dmaluka@chromium.org>,
Jinhui Guo <guojinhui.liam@bytedance.com>,
iommu@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: [PATCH 3/7] iommu/vt-d: Flush cache for PASID table before using it
Date: Thu, 22 Jan 2026 09:48:52 +0800 [thread overview]
Message-ID: <20260122014856.2457052-4-baolu.lu@linux.intel.com> (raw)
In-Reply-To: <20260122014856.2457052-1-baolu.lu@linux.intel.com>
From: Dmytro Maluka <dmaluka@chromium.org>
When writing the address of a freshly allocated zero-initialized PASID
table to a PASID directory entry, do that after the CPU cache flush for
this PASID table, not before it, to avoid the time window when this
PASID table may be already used by non-coherent IOMMU hardware while
its contents in RAM is still some random old data, not zero-initialized.
Fixes: 194b3348bdbb ("iommu/vt-d: Fix PASID directory pointer coherency")
Signed-off-by: Dmytro Maluka <dmaluka@chromium.org>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Link: https://lore.kernel.org/r/20251221123508.37495-1-dmaluka@chromium.org
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
drivers/iommu/intel/pasid.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index 99692f88b883..6379b211f12b 100644
--- a/drivers/iommu/intel/pasid.c
+++ b/drivers/iommu/intel/pasid.c
@@ -153,6 +153,9 @@ static struct pasid_entry *intel_pasid_get_entry(struct device *dev, u32 pasid)
if (!entries)
return NULL;
+ if (!ecap_coherent(info->iommu->ecap))
+ clflush_cache_range(entries, VTD_PAGE_SIZE);
+
/*
* The pasid directory table entry won't be freed after
* allocation. No worry about the race with free and
@@ -165,10 +168,8 @@ static struct pasid_entry *intel_pasid_get_entry(struct device *dev, u32 pasid)
iommu_free_pages(entries);
goto retry;
}
- if (!ecap_coherent(info->iommu->ecap)) {
- clflush_cache_range(entries, VTD_PAGE_SIZE);
+ if (!ecap_coherent(info->iommu->ecap))
clflush_cache_range(&dir[dir_index].val, sizeof(*dir));
- }
}
return &entries[index];
--
2.43.0
next prev parent reply other threads:[~2026-01-22 1:51 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-22 1:48 [PATCH 0/7] [PULL REQUEST] Intel IOMMU updates for v6.20 Lu Baolu
2026-01-22 1:48 ` [PATCH 1/7] iommu/vt-d: Skip dev-iotlb flush for inaccessible PCIe device without scalable mode Lu Baolu
2026-01-22 1:48 ` [PATCH 2/7] iommu/vt-d: Flush dev-IOTLB only when PCIe device is accessible in " Lu Baolu
2026-01-22 1:48 ` Lu Baolu [this message]
2026-01-22 1:48 ` [PATCH 4/7] iommu/vt-d: Flush piotlb for SVM and Nested domain Lu Baolu
2026-01-22 1:48 ` [PATCH 5/7] iommu/vt-d: Clear Present bit before tearing down PASID entry Lu Baolu
2026-01-22 1:48 ` [PATCH 6/7] iommu/vt-d: Clear Present bit before tearing down context entry Lu Baolu
2026-01-22 1:48 ` [PATCH 7/7] iommu/vt-d: Fix race condition during PASID entry replacement Lu Baolu
2026-01-22 8:20 ` [PATCH 0/7] [PULL REQUEST] Intel IOMMU updates for v6.20 Joerg Roedel
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