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[142.162.112.119]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-899c7193227sm41395436d6.21.2026.02.27.05.18.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Feb 2026 05:18:15 -0800 (PST) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1vvxjT-00000000uvx-0Dij; Fri, 27 Feb 2026 09:18:15 -0400 Date: Fri, 27 Feb 2026 09:18:15 -0400 From: Jason Gunthorpe To: Xu Yilun Cc: Sean Christopherson , Ackerley Tng , Alexey Kardashevskiy , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Kevin Tian , Joerg Roedel , Will Deacon , Robin Murphy , Paolo Bonzini , Steve Sistare , Nicolin Chen , iommu@lists.linux.dev, linux-coco@lists.linux.dev, Dan Williams , Santosh Shukla , "Pratik R . Sampat" , Fuad Tabba , "Aneesh Kumar K . V" , michael.roth@amd.com, vannapurve@google.com Subject: Re: [RFC PATCH kernel] iommufd: Allow mapping from KVM's guest_memfd Message-ID: <20260227131815.GG44359@ziepe.ca> References: <20260225075211.3353194-1-aik@amd.com> <20260226190757.GA44359@ziepe.ca> <20260227002105.GC44359@ziepe.ca> <20260227010902.GE44359@ziepe.ca> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Fri, Feb 27, 2026 at 06:35:44PM +0800, Xu Yilun wrote: > Will cause host machine check and host restart, same as host CPU > accessing encrypted memory. Intel TDX has no lower level privilege > protection table so the wrong accessing will actually impact the > memory encryption engine. Blah, of course it does. So Intel needs a two step synchronization to wipe the IOPTEs before any shared private conversions and restore the right ones after. AMD needs a nasty HW synchronization with RMP changes, but otherwise wants to map the entire physical space. ARM doesn't care much, I think it could safely do either approach? These are very different behaviors so I would expect that userspace needs to signal which of the two it wants. It feels like we need a fairly complex dedicated synchronization logic in iommufd coupled to the shared/private machinery in guestmemfd Not really sure how to implement the Intel version right now, it is sort of like a nasty version of SVA.. Jason