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[142.162.112.119]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-508f66da77csm51473791cf.30.2026.03.08.16.09.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Mar 2026 16:09:18 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1vzNFM-0000000Bzue-3rG7; Sun, 08 Mar 2026 20:09:16 -0300 Date: Sun, 8 Mar 2026 20:09:16 -0300 From: Jason Gunthorpe To: Leon Romanovsky Cc: Marek Szyprowski , Robin Murphy , "Michael S. Tsirkin" , Petr Tesarik , Jonathan Corbet , Shuah Khan , Jason Wang , Xuan Zhuo , Eugenio =?utf-8?B?UMOpcmV6?= , iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, virtualization@lists.linux.dev, linux-rdma@vger.kernel.org Subject: Re: [PATCH 2/3] dma-mapping: Clarify valid conditions for CPU cache line overlap Message-ID: <20260308230916.GI1687929@ziepe.ca> References: <20260307-dma-debug-overlap-v1-0-c034c38872af@nvidia.com> <20260307-dma-debug-overlap-v1-2-c034c38872af@nvidia.com> <20260308181920.GH1687929@ziepe.ca> <20260308184902.GR12611@unreal> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260308184902.GR12611@unreal> On Sun, Mar 08, 2026 at 08:49:02PM +0200, Leon Romanovsky wrote: > On Sun, Mar 08, 2026 at 03:19:20PM -0300, Jason Gunthorpe wrote: > > On Sat, Mar 07, 2026 at 06:49:56PM +0200, Leon Romanovsky wrote: > > > > > -This attribute indicates the CPU will not dirty any cacheline overlapping this > > > -DMA_FROM_DEVICE/DMA_BIDIRECTIONAL buffer while it is mapped. This allows > > > -multiple small buffers to safely share a cacheline without risk of data > > > -corruption, suppressing DMA debug warnings about overlapping mappings. > > > -All mappings sharing a cacheline should have this attribute. > > > +DMA_ATTR_CPU_CACHE_OVERLAP > > > > This is a very specific and well defined use case that allows some cache > > flushing behaviors to work only under the promise that the CPU doesn't > > touch the memory to cause cache inconsistencies. > > > > > +Another valid use case is on systems that are CPU-coherent and do not use > > > +SWIOTLB, where the caller can guarantee that no cache maintenance operations > > > +(such as flushes) will be performed that could overwrite shared cache lines. > > > > This is something completely unrelated. > > I disagree. The situation is equivalent in that callers guarantee the > CPU cache will not be overwritten. The RDMA callers do no such thing, they just don't work at all if there is non-coherence in the mapping which is why it is not a bug. virtio looks like it does actually keep the caches clean for different mappings (and probably also in practice forced coherent as well given qemu is coherent with the VM and VFIO doesn't allow non-coherent DMA devices) > > What I would really like is a new DMA_ATTR_REQUIRE_COHERENT which > > fails any mappings requests that would use any SWIOTLB or cache > > flushing. > > You are proposing something orthogonal that operates at a different layer > (DMA mapping). However, for DMA debugging, your new attribute will be > equivalent to DMA_ATTR_CPU_CACHE_OVERLAP. DMA_ATTR is a dma mapping flag, if you want some weird dma debugging flag it should be called DMA_ATTR_DEBUGGING_IGNORE_CACHELINES with some kind of statement at the user why it is OK. Jason