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[142.162.112.119]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8cda21346a0sm321675885a.34.2026.03.12.05.19.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2026 05:19:38 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1w0f0r-00000006esN-1WXU; Thu, 12 Mar 2026 09:19:37 -0300 Date: Thu, 12 Mar 2026 09:19:37 -0300 From: Jason Gunthorpe To: Leon Romanovsky Cc: Marek Szyprowski , Robin Murphy , "Michael S. Tsirkin" , Petr Tesarik , Jonathan Corbet , Shuah Khan , Jason Wang , Xuan Zhuo , Eugenio =?utf-8?B?UMOpcmV6?= , Steven Rostedt , Masami Hiramatsu , Mathieu Desnoyers , Joerg Roedel , Will Deacon , Andrew Morton , iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, virtualization@lists.linux.dev, linux-rdma@vger.kernel.org, linux-trace-kernel@vger.kernel.org, linux-mm@kvack.org Subject: Re: [PATCH v2 4/8] dma-mapping: Introduce DMA require coherency attribute Message-ID: <20260312121937.GD1469476@ziepe.ca> References: <20260311-dma-debug-overlap-v2-0-e00bc2ca346d@nvidia.com> <20260311-dma-debug-overlap-v2-4-e00bc2ca346d@nvidia.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260311-dma-debug-overlap-v2-4-e00bc2ca346d@nvidia.com> On Wed, Mar 11, 2026 at 09:08:47PM +0200, Leon Romanovsky wrote: > From: Leon Romanovsky > > The mapping buffers which carry this attribute require DMA coherent system. > This means that they can't take SWIOTLB path, can perform CPU cache overlap > and doesn't perform cache flushing. > > Signed-off-by: Leon Romanovsky > --- > Documentation/core-api/dma-attributes.rst | 12 ++++++++++++ > include/linux/dma-mapping.h | 7 +++++++ > include/trace/events/dma.h | 3 ++- > kernel/dma/debug.c | 3 ++- > kernel/dma/mapping.c | 6 ++++++ > 5 files changed, 29 insertions(+), 2 deletions(-) > > diff --git a/Documentation/core-api/dma-attributes.rst b/Documentation/core-api/dma-attributes.rst > index 48cfe86cc06d7..69d094f144c70 100644 > --- a/Documentation/core-api/dma-attributes.rst > +++ b/Documentation/core-api/dma-attributes.rst > @@ -163,3 +163,15 @@ data corruption. > > All mappings that share a cache line must set this attribute to suppress DMA > debug warnings about overlapping mappings. > + > +DMA_ATTR_REQUIRE_COHERENT > +------------------------- > + > +The mapping buffers which carry this attribute require DMA coherent system. This means > +that they can't take SWIOTLB path, can perform CPU cache overlap and doesn't perform > +cache flushing. DMA mapping requests with the DMA_ATTR_REQUIRE_COHERENT fail on any system where SWIOTLB or cache management is required. This should only be used to support uAPI designs that require continuous HW DMA coherence with userspace processes, for example RDMA and DRM. At a minimum the memory being mapped must be userspace memory from pin_user_pages() or similar. Drivers should consider using dma_mmap_pages() instead of this interface when building their uAPIs, when possible. It must never be used in an in-kernel driver that only works with kernal memory. > @@ -164,6 +164,9 @@ dma_addr_t dma_map_phys(struct device *dev, phys_addr_t phys, size_t size, > if (WARN_ON_ONCE(!dev->dma_mask)) > return DMA_MAPPING_ERROR; > > + if (!dev_is_dma_coherent(dev) && (attrs & DMA_ATTR_REQUIRE_COHERENT)) > + return DMA_MAPPING_ERROR; This doesn't capture enough conditions.. is_swiotlb_force_bounce(), dma_kmalloc_needs_bounce(), dma_capable(), etc all need to be blocked too So check it inside swiotlb_map() too, and maybe shift the above into the existing branches: if (!dev_is_dma_coherent(dev) && !(attrs & (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_MMIO))) arch_sync_dma_for_device(phys, size, dir); Jason