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From: Jason Gunthorpe <jgg@nvidia.com>
To: Wei Wang <wei.w.wang@hotmail.com>
Cc: iommu@lists.linux.dev, Joerg Roedel <joro@8bytes.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>,
	Will Deacon <will@kernel.org>,
	patches@lists.linux.dev
Subject: Re: [PATCH 1/5] iommu/amd: Simplify build_inv_address()
Date: Mon, 30 Mar 2026 09:05:00 -0300	[thread overview]
Message-ID: <20260330120500.GC310919@nvidia.com> (raw)
In-Reply-To: <SI2PR01MB439395C17C83A66A3E614470DC52A@SI2PR01MB4393.apcprd01.prod.exchangelabs.com>

On Mon, Mar 30, 2026 at 03:39:16PM +0800, Wei Wang wrote:

> > @@ -1267,39 +1267,37 @@ static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
> >    */
> >   static inline u64 build_inv_address(u64 address, size_t size)
> >   {
> > -	u64 pages, end, msb_diff;
> > +	u64 last = address + size - 1;
> > +	unsigned int sz_lg2;
> 
> Would naming it shift (or order) be more conventional?

I find that confusing, shift of what exactly? It is size of the
invalidation encoded in log 2.

> > -	end = address + size - 1;
> > +	address &= GENMASK_U64(63, 12);
> > +	sz_lg2 = fls64(address ^ last);
> > +	if (sz_lg2 <= 12)
> 
> then could use "if (shift < PAGE_SHIFT)" here.

PAGE_SHIFT defines the kernel mm configuration, "12" is a hardware
constant from the iommu spec. They should not be intermixed.
 
> > +		return address;
> >   	/*
> > -	 * msb_diff would hold the index of the most significant bit that
> > -	 * flipped between the start and end.
> > +	 * Encode sz_lg2 according to Table 14: Example Page Size Encodings
> > +	 *
> > +	 * See "Note *":
> > +	 *   Address bits 51:32 can be used to encode page sizes greater
> > +	 *   that 4 Gbytes.
> 
> "than" (seems a spec typo)

Yeah, I'll leave it as is.
 
> > +	 * Which we take to mean that the highest page size has bit
> > +	 *  [51]=0, [50:12]=1
> > +	 * and that coding happens when sz_lg2 is 52. Fall back to full
> > +	 * invalidation if the size is too big.
> > +	 *
> >   	 */
> > -	msb_diff = fls64(end ^ address) - 1;
> > +	if (unlikely(sz_lg2 > 52))
> > +		return (CMD_INV_IOMMU_ALL_PAGES_ADDRESS & PAGE_MASK) |
> > +		       CMD_INV_IOMMU_PAGES_SIZE_MASK;
> 
> 
> The spec mentions "Address bits 63:52 are zero-extended.", should we enforce
> it:
> 
> -#define CMD_INV_IOMMU_ALL_PAGES_ADDRESS        0x7ffffffffffff000ULL
> +#define CMD_INV_IOMMU_ALL_PAGES_ADDRESS        GENMASK_ULL(51, 12)
> 
> also for the returned "address"

2.4.3 specifically calls out 

 The IOMMU invalidates all translation
 information associated with the DomainID for both nested and guest levels when S=1, PDE=1,
 GN=0, and Address[63:12]=7_FFFF_FFFF_FFFFh.

I wouldn't change it.

Jason

  reply	other threads:[~2026-03-30 12:05 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-27 15:23 [PATCH 0/5] Improve the invalidation path in AMD Jason Gunthorpe
2026-03-27 15:23 ` [PATCH 1/5] iommu/amd: Simplify build_inv_address() Jason Gunthorpe
2026-03-30  7:39   ` Wei Wang
2026-03-30 12:05     ` Jason Gunthorpe [this message]
2026-03-31  2:01       ` Wei Wang
2026-03-27 15:23 ` [PATCH 2/5] iommu/amd: Pass last in through to build_inv_address() Jason Gunthorpe
2026-03-30  8:03   ` Wei Wang
2026-04-01 19:55     ` Jason Gunthorpe
2026-03-27 15:23 ` [PATCH 3/5] iommu/amd: Have amd_iommu_domain_flush_pages() use last Jason Gunthorpe
2026-04-01  6:33   ` Wei Wang
2026-03-27 15:23 ` [PATCH 4/5] iommu/amd: Make CMD_INV_IOMMU_ALL_PAGES_ADDRESS match the spec Jason Gunthorpe
2026-04-01  6:42   ` Wei Wang
2026-04-01 13:17     ` Jason Gunthorpe
2026-03-27 15:23 ` [PATCH 5/5] iommu/amd: Control INVALIDATE_IOMMU_PAGES PDE from the gather Jason Gunthorpe
2026-04-01  8:51   ` Wei Wang

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