Re: [PATCH 1/4] iommu/intel: Split piotlb invalidation into range and all

[Jason Gunthorpe <jgg@nvidia.com>]

On Mon, Mar 30, 2026 at 02:39:50PM +0800, Baolu Lu wrote:
> >   static void qi_batch_add_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid,
> >   				u64 addr, unsigned long npages, bool ih,
> >   				struct qi_batch *batch)
> >   {
> > -	/*
> > -	 * npages == -1 means a PASID-selective invalidation, otherwise,
> > -	 * a positive value for Page-selective-within-PASID invalidation.
> > -	 * 0 is not a valid input.
> > -	 */
> >   	if (!npages)
> >   		return;
> 
> The WARN_ON(!npages) logic is removed from the previous
> qi_flush_piotlb() (see below ...). Could it be added here to keep the
> "npages != 0" check?

The later patches remove this check entirely so I don't think we
should add a WARN_ON then remove it again..

> > @@ -1168,6 +1166,7 @@ void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
> >   void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
> >   			u16 qdep, u64 addr, unsigned mask);
> > +void qi_flush_piotlb_all(struct intel_iommu *iommu, u16 did, u32 pasid);
> 
> [...]
> 
> >   void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,
> >   		     unsigned long npages, bool ih);
> 
> qi_flush_piotlb() has been removed by this patch. Therefore above
> declaration should also be cleaned.

Ooops that hunk got into a later patch, I shifted it back

Thanks,
Jason