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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?bO3ZZXnubLz/+SmN2/usIWMBUKD3XznyuYs2CYG2oRzWK7iFSQjVOI6TjRU8?= =?us-ascii?Q?uSKoAZ+jhhOhH9f1pkPDznOYES30lNBlR99laEKARSwSVNaOIQ6ARwBc5e1p?= =?us-ascii?Q?xOX1rLDTO7/IEL+M7YfDt8IZI5Co0/T/zP8hzkGATViXGw7xhpHje9CcaG+u?= =?us-ascii?Q?+wLAzCRX3dw+NZn9QyUJ+zeA4dGldRBEhErb+69GcnoWkykBZnoVt/1+V/bb?= =?us-ascii?Q?BqXi5d7njFE07pH0uUxSmxiB+gtMhEa/ppwYDiEBLa1yZlnw1ah4CFIUtVKG?= =?us-ascii?Q?OzTemz9ZmQWxG9KIoG2Xf7WDyZqIP4PazG7RPZwDDjlAEAfuD0INtBRKphXB?= =?us-ascii?Q?duzF0RMxxnHcbu/zYIHePz8MfMrlvDxW/s5JDNZQGW5OQOg+wX1nC1UaVoOg?= =?us-ascii?Q?wGd+5wa6dZ3ZhJ06K24gddX2InBGFT4sws5YOJ/5AMLTDJ6YRp6O4sVA6SRN?= =?us-ascii?Q?L3CX74JVIOJ56Jn4LLVdRPRO71XTfQM1dL5CsayNcYlllALjSXh4WyN4xrPG?= =?us-ascii?Q?x+/eOdrwB7FDJLqwzVY1JGUiY2LF60rijclgZqQUBKNhqB+Lwf/wVknt6SE0?= =?us-ascii?Q?ddki3nPT72ojdrqjUA+vI7BBQQr0HLYHyADwT/LfVtWhzPeyUeDc7r/k8cNi?= =?us-ascii?Q?0XwzRb6WMlzN6LP+N1YhnAZoRG71oeHdP053WF03RnmtGhf6DecncL13CGMK?= =?us-ascii?Q?MzGs+auagCV9KC8SE7yqjFkqSFuQpakEYIAVRcscja3gKeG9nUJ8kLIxC2iB?= =?us-ascii?Q?QjS1TnlVV56hUzMs83Ziyg2V3IcLDmbE42mTp6uzEuuBHxiC+aELNm7GYFFi?= =?us-ascii?Q?kIhrQt0aEJ0OanUt/VYrBW3K5MmPifAefbmv9yTrc9GMSmeAdujSKrXfNA46?= =?us-ascii?Q?uDEGnJ4IY5pP7O0KOM/u/RCdcL9wwDxklfcyhTsnHnCaOUef3TBJuJ/tM9d7?= =?us-ascii?Q?y10zqn8KGZNFdgeSkesEyIy5NVDR3vWf3M7JpYhtPDiGUPYysT0+kt4s1n3a?= =?us-ascii?Q?7scIdjYNnY/hbbkdHLDScj4/tI/PEpaSnRujfQDINl9ftuCl/xzu0Gj/oqj9?= =?us-ascii?Q?sFpPvt71/1mUTeKZOQU0J/TgeUYYIeR0wBk7Fx8nL/3T7oJ3bggqepX8e7yq?= =?us-ascii?Q?gy8rjTKeEvmUVWUotvMkcbblwPPoHP8KTkMWJcqqRO74BETGCuJAxkuoOc6U?= =?us-ascii?Q?RkNk8A/GbHONygtFdtCY6d5PPW67cjlvFTehPdvE8YoDXcSEA+GdVVkT7SJ6?= =?us-ascii?Q?Q+jfklICxuoFQlOGzxnre9pUhksRWVlaY4iYxpetc5XDn4vscIOIb5QTvjq8?= =?us-ascii?Q?kyJy9J2TQ8/olqpj7cWrIIm5omwSuHyJsfBJzMe9/XmB3ePvbcB36B0uc3sF?= =?us-ascii?Q?y8MJBT8DK6MoTJY7O1fBFcoY1eq7K2RScM3DboOg6l73yWv87JYp4UsdKGC1?= =?us-ascii?Q?Lk11i+vfovj4rhAcH8a9FJJm/y9Xrn6GVb5fLFO4q1Gy1aSxdYBg08D6LOGp?= =?us-ascii?Q?/pA5oOdilsYMhPCaoVvjlLJAaMRd/6W5Bb/NKP9D7Zry/gN2tGJwlnEggrmS?= =?us-ascii?Q?TzVEw+G9fsk6mzvGYB7S146Ub4/ZUm7cIE9odrTkFVLtlJa7C3k/2AGIlEzz?= =?us-ascii?Q?qK4i9LetVZP72gGWe+Kul1mUDgoM2UgIM56lVssQAxeNAIwmL6P9ZXnPziVg?= =?us-ascii?Q?mnzFoN2qdrmnEVvI4o7RZGJ+cpbhZpUPR9uftzjTy4Ah2PYz+MMynXtA/Aor?= =?us-ascii?Q?N5dfo4vESA=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: e9af5cdc-52dc-411a-1f4e-08def47ab67e X-MS-Exchange-CrossTenant-AuthSource: LV8PR12MB9620.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2026 11:55:02.0055 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 0pRUIC2X8wbPDDTrnFBiTffTloIMZCjnZXiBsiyrZAsZOHGa/K8NG/UhNVjtwzrc X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7565 On Fri, Aug 07, 2026 at 12:03:14PM +0100, Robin Murphy wrote: > > Each struct device will have a flag that shows if it is in T=1 or T=0 > > state. The flag can only change while a driver is not bound, and > > changing the flag will update the DMA API configuration. > > I see we no longer seem to have the concern of devices in TDISP RUN state > being able to send T=0 transactions other than MSI writes, Right it was too complex and nobody needed it, so Linux will not support T=0 through the DMA API on an T=1 device, and devices should be designed to only send T=1 to the greatest degree possible. If someone foolishly makes a device that works otherwise they will have to take the difficult SW tasks of making it work. > where GICv3 means the host is already going to have to be in on the > game to some degree there anyway. As I understand it: We will need to teach GIC to understand if/when the device uses a T=0 translation for MSI and then use a shared physical address for the ITS IOVA instead of getting an IOVA translation from the iommu. The hypervisor will setup the S2 for the T=0 SMMU translation to be identity with all shared memory and the ITS page will be shared memory. Presumably in future we will have HW to handle a T=1 ITS page access and some way to negotiate with devices if they should use a T=1 path for MSI or not. There won't be a vSMMU attached to the T=0 instance at all, it is just wired to be bypass. > support in firmware bindings nor the IOMMU API itself to be able to describe > a single device being associated with both the RMM's vSMMU for the T=1 > (Realm) VA space, and the NS VMM's vSMMU for the T=0 VA space, even > if we Right! > did only have to care about using strictly one or the other at any given > time based on device state. Having distinct struct devices is indeed clunky, > but does at least reduce the problem to a currently-manageable one of the > client driver having to wrangle them as a pair. So hard! A meaningful goal here is to have existing drivers largely work unchanged in a CC world, so the device starts doing T=1 for almost everything and the existing driver just works. > (And FWIW when we do get there, I'd be inclined to make the default SWIOTLB > the "private" one, so all the sharing/decryption stuff can be neatly > partitioned off into the CoCo etc. special cases...) Yeah Jason