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[159.2.239.150]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-91bcba4db4csm8430526d6.16.2026.10.15.16.55.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2026 16:55:35 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1xHVIM-00000000Gew-3ViJ; Thu, 15 Oct 2026 20:55:34 -0300 Date: Thu, 15 Oct 2026 20:55:34 -0300 From: Jason Gunthorpe To: Gong Shuai Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Tomasz Jeznach , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Paolo Bonzini , Sean Christopherson , Kevin Tian , Andrew Jones , Fangyu Yu , Wu Fei , Zhao Qingye , Gong Shuai Subject: Re: [RFC PATCH 07/12] iommufd: Add RISC-V IOMMU hardware info type Message-ID: <20261015235534.GA14213@ziepe.ca> References: <20261015065232.604503-1-gong.shuai@sanechips.com.cn> <20261015065232.604503-8-gong.shuai@sanechips.com.cn> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261015065232.604503-8-gong.shuai@sanechips.com.cn> On Thu, Oct 15, 2026 at 02:52:27PM +0800, Gong Shuai wrote: > From: Wu Fei > > Add IOMMU_HW_INFO_TYPE_RISCV and struct iommu_hw_info_riscv, which > reports the RISC-V IOMMU Capabilities register through > IOMMU_GET_HW_INFO. > > Signed-off-by: Wu Fei > Signed-off-by: Gong Shuai > --- > include/uapi/linux/iommufd.h | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h > index 36e6187bb34b..acfef0338cd1 100644 > --- a/include/uapi/linux/iommufd.h > +++ b/include/uapi/linux/iommufd.h > @@ -716,6 +716,14 @@ struct iommu_hw_info_amd { > __aligned_u64 efr2; > }; > > +/** > + * struct iommu_hw_info_riscv - RISC-V IOMMU device info > + * @capabilities: Value of RISC-V IOMMU Capabilities register > + */ > +struct iommu_hw_info_riscv { > + __u64 capabilities; > +}; > + Same here, spec reference. Also be careful to always use __aligned_u64, check all the patches. JAson