From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=95.215.58.30 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1792683986; b=gkUL5tIKyKDKQCYxxKDFkON9tBRjf2H9sAlzG7I3UvVa6Lc6/ipKjkPFXEohqNEmR7GQ 9zaM07U97dhue1h73ELMVBBwP7gry4DVnMWRB2NJ11B58yD0mCtkznL3hA/HilzDv2N8p QUm992uJYxk56n8ZqWwffVIlpWtwkDamHiC+7aDfEJhHuaLYqrzLJ7IIpjTHi68u94V6K cRMw7JNQBz9H6J6hTS/rPWzWdBb0USIJgMQjoWMgQMLJjWhQz2HY/je6A0Ha8IA3lMUXP kTVFDWZXOnZlguk7ufiVAG5xyEZH+OQWBUDVYTPPpcHgLEsEzzUgcp6YDB6cXZWJS8Q== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1792683986; h=DMARC-Filter:X-Envelope-To:DKIM-Signature:X-Envelope-To:Received: X-Mizu-Trace-ID:X-Migadu-Flow:From:To:Cc:Subject:Date:Message-ID: X-Mailer:In-Reply-To:References:MIME-Version: Content-Transfer-Encoding; bh=nDyFWuaOVRtQbtncMRtG13mndwFTM1P70HEBebNl9Oo=; b=Rt5J9rTu/h5+79MSZXVAaAqYcy8YOrpRs3HvdMbv3ankpnzH9nh0thgcqtLgIwvWj8KD ow5LFA/E7M1tzSQKmgLN4Se+1WVDtcP7zD16deJ+nt8Zd17OH5dZgaVer6N3xzAz9W3oN Mb5oB2DMcFy2DmhKBXRjdgOql4k9eAeziFPX91wysTEUjSSp4aOq9UiJwtDfM24csi+ms BpHAdW0epGZzrjnPo8Rs4pgRsGi/Qkao3k2waFX78q+2PgQkrEsm52VzJElvrTsSHoeFh p5eUJWxYnqNR4rTFF2NLSFpsTKTmghc18xV7sTHR8iMj+boeIK96MAmiLkaO5WY3f9g== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass header.d=linux.dev header.i=@linux.dev header.a=rsa-sha256 header.s=key1 header.b=dfiC4SjV; arc=none smtp.remote-ip=95.215.58.30 Received: from mta1.migadu.com (out-30.mta1.migadu.com [95.215.58.30]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0C57606A31D for ; Thu, 22 Oct 2026 15:46:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.2 smtp.subspace.kernel.org D0C57606A31D Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key, unprotected) header.d=linux.dev header.i=@linux.dev header.a=rsa-sha256 header.s=key1 header.b=dfiC4SjV X-Envelope-To: iommu@lists.linux.dev DKIM-Signature: a=rsa-sha256; bh=IgnvtTm5S8xUMQvtkLK6nhnCRAcGmQUfy+GHyDb3GiI=; c=simple/simple; d=linux.dev; h=from:to:subject:date:message-id:mime-version:content-type; s=key1; t=1792683983; v=1; x=1793288783; b=dfiC4SjVXaOPaXZGvRWmSNmfPSrnEWZQWj0PCP95FV5KqrHi3Z8tHHDwMwyBB2b7Pb2BVHiW s7qSn1/ky0KnGCSHhNYIko4YpiSZfLU4a2W0Y24CQoeC/MoB+Epi+/QplecOvYzKbhBJlIrvHfj c+ngY6lN1nf+VOo4GZkmkWZU= X-Envelope-To: iommu@lists.linux.dev Received: by smtp.migadu.com with ESMTPS id 6021e6b73b548721; Thu, 22 Oct 2026 15:46:23 +0000 X-Mizu-Trace-ID: 6021e6b73b548721 X-Migadu-Flow: FLOW_OUT From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com, nutty.liu@hotmail.com Subject: [PATCH v7 4/5] irqchip/riscv-imsic: Support IOMMU MSI address lists Date: Thu, 22 Oct 2026 17:46:02 +0200 Message-ID: <20261022154603.1374754-5-andrew.jones@linux.dev> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261022154603.1374754-1-andrew.jones@linux.dev> References: <20261022154603.1374754-1-andrew.jones@linux.dev> X-Mailing-List: iommu@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Andrew Jones RISC-V IOMMU host interrupt remapping maps every possible host IMSIC target into one contiguous IOVA range. MSI message composition therefore needs each target's position within that range. Prepare the complete IMSIC address list while allocating an IRQ. The list is guaranteed to exist after IMSIC state initialization. The IOMMU backend maps the pages and caches the contiguous base IOVA in the MSI descriptor when translation is needed. When the descriptor has an IOMMU MSI mapping, use the selected logical CPU directly as the page index within the IOVA range. Use the same path for initial composition and affinity updates. A zero iommu_msi_shift means no MSI address translation is required, so keep physical messages. Signed-off-by: Andrew Jones Signed-off-by: Andrew Jones Tested-by: Fangyu Yu Acked-by: Thomas Gleixner Reviewed-by: Nutty Liu Reviewed-by: Anup Patel Acked-by: Anup Patel --- drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-riscv-imsic-platform.c | 24 +++++++++++++++++++--- 2 files changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 20b77fbc51ee..a038e1121be3 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -651,6 +651,7 @@ config RISCV_IMSIC select IRQ_DOMAIN_HIERARCHY select GENERIC_IRQ_MATRIX_ALLOCATOR select GENERIC_MSI_IRQ + select IRQ_MSI_IOMMU select IRQ_MSI_LIB config RISCV_RPMI_SYSMSI diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/irq-riscv-imsic-platform.c index 643c8e459611..ddb2bb570cdc 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -69,8 +70,10 @@ static void imsic_irq_ack(struct irq_data *d) irq_move_irq(d); } -static void imsic_irq_compose_vector_msg(struct imsic_vector *vec, struct msi_msg *msg) +static void imsic_irq_compose_vector_msg(struct irq_data *d, struct imsic_vector *vec, + struct msi_msg *msg) { + struct msi_desc *desc = irq_data_get_msi_desc(d); phys_addr_t msi_addr; if (WARN_ON(!vec)) @@ -79,6 +82,12 @@ static void imsic_irq_compose_vector_msg(struct imsic_vector *vec, struct msi_ms if (WARN_ON(!imsic_cpu_page_phys(vec->cpu, 0, &msi_addr))) return; + /* A zero shift means no IOMMU MSI mapping is needed. */ + if (desc->iommu_msi_shift) { + msi_addr = (desc->iommu_msi_iova << desc->iommu_msi_shift) + + vec->cpu * IMSIC_MMIO_PAGE_SZ; + } + msg->address_hi = upper_32_bits(msi_addr); msg->address_lo = lower_32_bits(msi_addr); msg->data = vec->local_id; @@ -86,7 +95,7 @@ static void imsic_irq_compose_vector_msg(struct imsic_vector *vec, struct msi_ms static void imsic_irq_compose_msg(struct irq_data *d, struct msi_msg *msg) { - imsic_irq_compose_vector_msg(irq_data_get_irq_chip_data(d), msg); + imsic_irq_compose_vector_msg(d, irq_data_get_irq_chip_data(d), msg); } #ifdef CONFIG_SMP @@ -94,7 +103,7 @@ static void imsic_msi_update_msg(struct irq_data *d, struct imsic_vector *vec) { struct msi_msg msg = { }; - imsic_irq_compose_vector_msg(vec, &msg); + imsic_irq_compose_vector_msg(d, vec, &msg); irq_data_get_irq_chip(d)->irq_write_msi_msg(d, &msg); } @@ -225,7 +234,9 @@ static struct irq_chip imsic_irq_base_chip = { static int imsic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs, void *args) { + msi_alloc_info_t *info = args; struct imsic_vector *vec; + int ret; /* Multi-MSI is not supported yet. */ if (nr_irqs > 1) @@ -235,6 +246,13 @@ static int imsic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, if (!vec) return -ENOSPC; + ret = iommu_dma_prepare_msi_list(info->desc, imsic->msi_pa_list, + num_possible_cpus(), IMSIC_MMIO_PAGE_SZ); + if (ret) { + imsic_vector_free(vec); + return ret; + } + irq_domain_set_info(domain, virq, virq, &imsic_irq_base_chip, vec, handle_edge_irq, NULL, NULL); irq_set_noprobe(virq); -- 2.56.0