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[178.235.177.17]) by smtp.gmail.com with ESMTPSA id s5-20020a170906454500b009c7608eb499sm1878707ejq.94.2023.11.04.04.30.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 04 Nov 2023 04:30:55 -0700 (PDT) Message-ID: <26af3ecc-8b3f-4b10-b594-eae57de501cb@linaro.org> Date: Sat, 4 Nov 2023 12:30:54 +0100 Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] iommu/arm-smmu: re-enable context caching in smmu reset operation Content-Language: en-US To: Bibek Kumar Patro , will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, dmitry.baryshkov@linaro.org, a39.skl@gmail.com, quic_saipraka@quicinc.com, quic_pkondeti@quicinc.com, quic_molvera@quicinc.com Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, qipl.kernel.upstream@quicinc.com References: <20231103215124.1095-1-quic_bibekkum@quicinc.com> <20231103215124.1095-4-quic_bibekkum@quicinc.com> From: Konrad Dybcio In-Reply-To: <20231103215124.1095-4-quic_bibekkum@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 11/3/23 22:51, Bibek Kumar Patro wrote: > Context caching is re-enabled in the prefetch buffer for Qualcomm SoCs > through SoC specific reset ops, which is disabled in the default MMU-500 > reset ops, but is expected for context banks using ACTLR register to > retain the prefetch value during reset and runtime suspend. > > Signed-off-by: Bibek Kumar Patro > --- > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 26 ++++++++++++++++++---- > 1 file changed, 22 insertions(+), 4 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index 590b7c285299..f342b4778cf1 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -457,11 +457,29 @@ static int qcom_smmu_def_domain_type(struct device *dev) > return match ? IOMMU_DOMAIN_IDENTITY : 0; > } > > +#define ARM_MMU500_ACTLR_CPRE BIT(1) > + > +static int qcom_smmu500_reset(struct arm_smmu_device *smmu) > +{ > + int i; > + u32 reg; > + > + arm_mmu500_reset(smmu); > + > + for (i = 0; i < smmu->num_context_banks; ++i) { This loop deserves a comment above it like /* Re-enable context caching after reset */ Konrad