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[2001:678:a5c:1202:2659:d6e4:5d55:b864]) by smtp.gmail.com with ESMTPSA id c3-20020ac244a3000000b00515bad4cd0asm1524209lfm.155.2024.05.06.00.47.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 06 May 2024 00:47:51 -0700 (PDT) Message-ID: <2a0d574d-6a3b-4344-9571-840eee569ae1@gmail.com> Date: Mon, 6 May 2024 09:47:50 +0200 Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 07/15] iommu/amd: Setup GCR3 table in advance if domain is SVA capable To: Vasant Hegde , iommu@lists.linux.dev, joro@8bytes.org Cc: suravee.suthikulpanit@amd.com, wei.huang2@amd.com, jsnitsel@redhat.com, jgg@ziepe.ca, Jason Gunthorpe References: <20240418103400.6229-1-vasant.hegde@amd.com> <20240418103400.6229-8-vasant.hegde@amd.com> <333e6eb6-361c-4afb-8107-2573324bf689@gmail.com> <3488f733-c920-4e2a-86f7-05dc1779685e@amd.com> Content-Language: en-US, sv-SE From: Klara Modin In-Reply-To: <3488f733-c920-4e2a-86f7-05dc1779685e@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 2024-05-06 09:31, Vasant Hegde wrote: > Hi Klara, > > Thanks for the report. > > Looking into the attached dmesg : > > 2024-04-29T10:35:05+02:00 soda.int.kasm.eu kernel: AMD-Vi: Using global IVHD > EFR:0x0, EFR2:0x0 > > --> This means BIOS didn't setup the EFR flags in ACPI IVRS table (its BIOS issue). > > Commit 8e0179733172 (iommu/amd: Enable Guest Translation before registering > devices) changed GT feature enablement in control register. > > Now it tries to enable CONTROL[GT] flag before reading IOMMU feature register > (late_iommu_features_init()). > > In attach device path, it assumed GT is supported (based on IOMMU EFR register > value) and enabled DTE[GV]. Hence we hit ILLEGAL_DEV_TABLE_ENTRY error. > > > Can you please try below fix? > > > -Vasant > > --- > > > diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c > index fd3e76e43699..b292181995b7 100644 > --- a/drivers/iommu/amd/init.c > +++ b/drivers/iommu/amd/init.c > @@ -2046,6 +2046,8 @@ static int __init iommu_init_pci(struct amd_iommu *iommu) > amd_iommu_max_glx_val = glxval; > else > amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval); > + > + iommu_enable_gt(iommu); > } > > if (check_feature(FEATURE_PPR) && amd_iommu_alloc_ppr_log(iommu)) > @@ -2732,7 +2734,6 @@ static void early_enable_iommu(struct amd_iommu *iommu) > iommu_enable_command_buffer(iommu); > iommu_enable_event_buffer(iommu); > iommu_set_exclusion_range(iommu); > - iommu_enable_gt(iommu); > iommu_enable_ga(iommu); > iommu_enable_xt(iommu); > iommu_enable_irtcachedis(iommu); > @@ -2789,7 +2790,6 @@ static void early_enable_iommus(void) > iommu_disable_irtcachedis(iommu); > iommu_enable_command_buffer(iommu); > iommu_enable_event_buffer(iommu); > - iommu_enable_gt(iommu); > iommu_enable_ga(iommu); > iommu_enable_xt(iommu); > iommu_enable_irtcachedis(iommu); This fixes the issue for me. Thanks, Tested-by: Klara Modin