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Wed, 06 Jul 2022 12:02:53 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 6 Jul 2022 12:02:52 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 6 Jul 2022 12:02:52 +0800 Message-ID: <2a6619e4e93f09dfae32d33aae968adcad0cf482.camel@mediatek.com> Subject: Re: [PATCH v1 16/16] arm64: dts: mt8195: Add display node for vdosys0 To: Krzysztof Kozlowski , Yong Wu , Joerg Roedel , Will Deacon , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Chun-Jie Chen , AngeloGioacchino Del Regno , "Enric Balletbo i Serra" , Weiyi Lu Date: Wed, 6 Jul 2022 12:02:52 +0800 In-Reply-To: <27c8f7b1-c308-89c2-54be-2d6c1a5527b8@linaro.org> References: <20220704100028.19932-1-tinghan.shen@mediatek.com> <20220704100028.19932-17-tinghan.shen@mediatek.com> <27c8f7b1-c308-89c2-54be-2d6c1a5527b8@linaro.org> X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 X-MTK: N Cc: devicetree@vger.kernel.org, "Jason-JH.Lin" , linux-kernel@vger.kernel.org, Project_Global_Chrome_Upstream_Group@mediatek.com, iommu@lists.linux-foundation.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Tinghan Shen via iommu Reply-To: Tinghan Shen Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Mon, 2022-07-04 at 14:39 +0200, Krzysztof Kozlowski wrote: > On 04/07/2022 12:00, Tinghan Shen wrote: > > From: "Jason-JH.Lin" > > > > Add display node for vdosys0 of mt8195. > > > > Signed-off-by: Jason-JH.Lin > > Signed-off-by: Tinghan Shen > > --- > > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 109 +++++++++++++++++++++++ > > 1 file changed, 109 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > index 724c6ca837b6..faea8ef33e5a 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > @@ -1961,6 +1961,7 @@ > > vdosys0: syscon@1c01a000 { > > compatible = "mediatek,mt8195-mmsys", "syscon"; > > reg = <0 0x1c01a000 0 0x1000>; > > + mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; > > #clock-cells = <1>; > > }; > > > > @@ -1976,6 +1977,114 @@ > > power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; > > }; > > > > + ovl0: ovl@1c000000 { > > + compatible = "mediatek,mt8195-disp-ovl", > > + "mediatek,mt8183-disp-ovl"; > > + reg = <0 0x1c000000 0 0x1000>; > > + interrupts = ; > > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > > + clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; > > + iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; > > + mediatek,gce-client-reg = > > + <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; > > + }; > > + > > + rdma0: rdma@1c002000 { > > + compatible = "mediatek,mt8195-disp-rdma"; > > + reg = <0 0x1c002000 0 0x1000>; > > + interrupts = ; > > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > > + clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; > > + iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; > > + mediatek,gce-client-reg = > > + <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; > > + }; > > + > > + color0: color@1c003000 { > > + compatible = "mediatek,mt8195-disp-color", > > + "mediatek,mt8173-disp-color"; > > + reg = <0 0x1c003000 0 0x1000>; > > + interrupts = ; > > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > > + clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; > > + mediatek,gce-client-reg = > > + <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; > > + }; > > + > > + ccorr0: ccorr@1c004000 { > > + compatible = "mediatek,mt8195-disp-ccorr", > > + "mediatek,mt8192-disp-ccorr"; > > + reg = <0 0x1c004000 0 0x1000>; > > + interrupts = ; > > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > > + clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; > > + mediatek,gce-client-reg = > > + <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; > > + }; > > + > > + aal0: aal@1c005000 { > > + compatible = "mediatek,mt8195-disp-aal", > > + "mediatek,mt8183-disp-aal"; > > + reg = <0 0x1c005000 0 0x1000>; > > + interrupts = ; > > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > > + clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; > > + mediatek,gce-client-reg = > > + <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; > > + }; > > + > > + gamma0: gamma@1c006000 { > > + compatible = "mediatek,mt8195-disp-gamma", > > + "mediatek,mt8183-disp-gamma"; > > + reg = <0 0x1c006000 0 0x1000>; > > + interrupts = ; > > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > > + clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; > > + mediatek,gce-client-reg = > > + <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; > > + }; > > + > > + dither0: dither@1c007000 { > > + compatible = "mediatek,mt8195-disp-dither", > > + "mediatek,mt8183-disp-dither"; > > + reg = <0 0x1c007000 0 0x1000>; > > + interrupts = ; > > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > > + clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; > > + mediatek,gce-client-reg = > > + <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; > > + }; > > + > > + dsc0: dsc@1c009000 { > > + compatible = "mediatek,mt8195-disp-dsc"; > > + reg = <0 0x1c009000 0 0x1000>; > > + interrupts = ; > > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > > + clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; > > + mediatek,gce-client-reg = > > + <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; > > + }; > > + > > + merge0: merge0@1c014000 { > > Generic node name. > > > + compatible = "mediatek,mt8195-disp-merge"; > > + reg = <0 0x1c014000 0 0x1000>; > > + interrupts = ; > > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > > + clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; > > + mediatek,gce-client-reg = > > + <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; > > + }; > > + > > + mutex: mutex0@1c016000 { > > Generic node name. > > > + compatible = "mediatek,mt8195-disp-mutex"; > > + reg = <0 0x1c016000 0 0x1000>; > > + interrupts = ; > > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > > + clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; > > + mediatek,gce-events = > > + ; > > + }; > > + > > larb0: larb@1c018000 { > > compatible = "mediatek,mt8195-smi-larb"; > > reg = <0 0x1c018000 0 0x1000>; > > > Best regards, > Krzysztof Ok, I'll update in the next version. Thanks, TingHan _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu