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Tue, 20 Apr 2021 06:06:36 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 269CFC433D3; Tue, 20 Apr 2021 06:06:36 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5E8B9C433F1; Tue, 20 Apr 2021 06:06:35 +0000 (UTC) MIME-Version: 1.0 Date: Tue, 20 Apr 2021 11:36:35 +0530 From: Sai Prakash Ranjan To: Bjorn Andersson Subject: Re: [PATCHv2 2/2] iommu/arm-smmu-qcom: Move the adreno smmu specific impl earlier In-Reply-To: <20210419143802.GP1538589@yoga> References: <20210419143802.GP1538589@yoga> Message-ID: <2b940e7f483b567b8e0b3f0ce657b453@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Cc: Will Deacon , Akhil P Oommen , iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Jordan Crouse , linux-arm-msm@vger.kernel.org, Robin Murphy , linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On 2021-04-19 20:08, Bjorn Andersson wrote: > On Fri 26 Feb 03:55 CST 2021, Sai Prakash Ranjan wrote: > >> Adreno(GPU) SMMU and APSS(Application Processor SubSystem) SMMU >> both implement "arm,mmu-500" in some QTI SoCs and to run through >> adreno smmu specific implementation such as enabling split pagetables >> support, we need to match the "qcom,adreno-smmu" compatible first >> before apss smmu or else we will be running apps smmu implementation >> for adreno smmu and the additional features for adreno smmu is never >> set. For ex: we have "qcom,sc7280-smmu-500" compatible for both apps >> and adreno smmu implementing "arm,mmu-500", so the adreno smmu >> implementation is never reached because the current sequence checks >> for apps smmu compatible(qcom,sc7280-smmu-500) first and runs that >> specific impl and we never reach adreno smmu specific implementation. >> >> Suggested-by: Akhil P Oommen >> Signed-off-by: Sai Prakash Ranjan > > Sorry for taking my time thinking about this. > > Reviewed-by: Bjorn Andersson > No worries, thanks Bjorn. -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu