public inbox for iommu@lists.linux-foundation.org
 help / color / mirror / Atom feed
From: Robin Murphy <robin.murphy@arm.com>
To: "Conor Dooley" <conor@kernel.org>, 郑律 <lv.zheng@spacemit.com>
Cc: Tomasz Jeznach <tjeznach@rivosinc.com>,
	Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>, Jingyu Li <joey.li@spacemit.com>,
	iommu <iommu@lists.linux.dev>,
	linux-perf-users <linux-perf-users@vger.kernel.org>,
	linux-riscv <linux-riscv@lists.infradead.org>,
	spacemit <spacemit@lists.linux.dev>,
	devicetree <devicetree@vger.kernel.org>
Subject: Re: [PATCH v1.1 4/7] dt-bindings: iommu: Add spacemit/t100 features
Date: Thu, 29 Jan 2026 17:06:00 +0000	[thread overview]
Message-ID: <2f1f48c6-ad75-4e7d-89a2-c93bb1c1d067@arm.com> (raw)
In-Reply-To: <20260129-grandly-compare-e8e3a105f690@spud>

On 29/01/2026 4:41 pm, Conor Dooley wrote:
> On Thu, Jan 29, 2026 at 06:43:03PM +0800, 郑律 wrote:
>>> From: "Conor Dooley"<conor@kernel.org>
>>> Date:  Thu, Jan 29, 2026, 18:08
>>> Subject:  Re: [PATCH v1.1 4/7] dt-bindings: iommu: Add spacemit/t100 features
>>> To: "Lv Zheng"<lv.zheng@spacemit.com>
>>> Cc: "Tomasz Jeznach"<tjeznach@rivosinc.com>, "Joerg Roedel"<joro@8bytes.org>, "Will Deacon"<will@kernel.org>, "Robin Murphy"<robin.murphy@arm.com>, "Rob Herring"<robh@kernel.org>, "Krzysztof Kozlowski"<krzk+dt@kernel.org>, "Conor Dooley"<conor+dt@kernel.org>, "Paul Walmsley"<pjw@kernel.org>, "Palmer Dabbelt"<palmer@dabbelt.com>, "Albert Ou"<aou@eecs.berkeley.edu>, "Alexandre Ghiti"<alex@ghiti.fr>, "Jingyu Li"<joey.li@spacemit.com>, "Zhijian Chen"<zhijian@spacemit.com>, <iommu@lists.linux.dev>, <linux-perf-users@vger.kernel.org>, <linux-riscv@lists.infradead.org>, <spacemit@lists.linux.dev>, <devicetree@vger.kernel.org>
>>> On Thu, Jan 29, 2026 at 02:09:13PM +0800, Lv Zheng wrote:
>>>> Adds device tree bindings for SpacemiT T100 specific features.
>>>>   
>>>> vendor-hpm-events: Allow vendor events to be customized in the device
>>>>                     tree.
>>>> global-filter: The feature saves silicon area by reducing filters to
>>>>                 one and use it as a global filter across all events.
>>>>                 This usually is sufficient for real applications.
>>>   
>>> Why can these not be determined from a device specific compatible?
>>
>> The specification only defines less than 10 standard event types while the
>> real silicons should have implemented many other event types based on
>> their micro-architecture. I tried to provide a common mechanism for all
>> vendor specific event types across different vendors.
> 
> Given that the variance is based on uarch, it sounds like it can be
> determined from the compatible.
> 
>> It is similar for the global filter, the global filter mechanism actually
>> complies to the IOMMU specification, users can alter the iohpmevt
>> registers as is what is specified in the IOMMU specification. It only
>> provides slight application difference between the final effection. Thus
>> this could also be a non-device specific option.
> 
> What is a "user" in this context? Given you're talking about reducing
> silicon area, it sounds like this will be set in stone for each SoC, and
> therefore can be determined by compatible. If other devices do this,
> they can also determine it from their compatible.
> 
> Properties for things that can be determined based on compatible are
> generally not permitted, so you'll need to provide a compelling
> rationale. Common mechanism isn't one, since determining based on
> compatible would be a common mechanism based on match data that people
> can tack onto for their devices.

Also, reinventing jevents via devicetree is pretty grim anyway - the PMU 
can simply expose an "identifier" attribute that uniquely identifies the 
vendor implementation, and perf tooling can match that to a set of event 
definitions in userspace, with the added bonus that jevents can also 
encode meaningful descriptions, metrics and suchlike. There doesn't 
*need* to be a sysfs alias for every possible event. I see the RISC-V 
CPU PMUs are already on-board with this approach - note the 
"Unit"/"Compat" matching for system/uncore PMUs is a little different 
from the mapfile used for CPUs, but see other architectures for examples.

Thanks,
Robin.


  reply	other threads:[~2026-01-29 17:06 UTC|newest]

Thread overview: 73+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-28  2:24 [PATCH 0/6] iommu/riscv: Add HPM support for RISC-V IOMMU Lv Zheng
2026-01-28  2:24 ` [PATCH 1/6] iommu/riscv: Enable IOMMU DMA mapping support Lv Zheng
2026-01-28  2:24 ` [PATCH 2/6] iommu/riscv: Fix WSI mode IRQ number handling Lv Zheng
2026-01-28  2:24 ` [PATCH 3/6] iommu/riscv: Add HPM support for performance monitoring Lv Zheng
2026-01-28  2:24 ` [PATCH 4/6] spacemit/t100: Add vendor event support for RISC-V IOMMU HPM Lv Zheng
2026-01-28  7:45   ` Krzysztof Kozlowski
2026-01-28  8:24     ` 郑律
2026-01-28  2:25 ` [PATCH 5/6] spacemit/t100: Add global filter " Lv Zheng
2026-01-28  7:46   ` Krzysztof Kozlowski
2026-01-28  8:23     ` 郑律
2026-01-28  2:25 ` [PATCH 6/6] spacemit/t100: Add SpacemiT T100 IOATC HPM support Lv Zheng
2026-01-29  6:08 ` [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU Lv Zheng
2026-01-29  6:08   ` [PATCH v1.1 1/7] iommu/riscv: Enable IOMMU DMA mapping support Lv Zheng
2026-01-29  6:08   ` [PATCH v1.1 2/7] iommu/riscv: Fix WSI mode IRQ number handling Lv Zheng
2026-01-29  6:08   ` [PATCH v1.1 3/7] iommu/riscv: Add HPM support for performance monitoring Lv Zheng
2026-01-29  6:09   ` [PATCH v1.1 4/7] dt-bindings: iommu: Add spacemit/t100 features Lv Zheng
2026-01-29 10:08     ` Conor Dooley
2026-01-29 10:43       ` 郑律
2026-01-29 16:41         ` Conor Dooley
2026-01-29 17:06           ` Robin Murphy [this message]
2026-01-30  1:30             ` 郑律
2026-01-30  1:39           ` 郑律
2026-01-29  6:09   ` [PATCH v1.1 5/7] spacemit/t100: Add vendor event support for RISC-V IOMMU HPM Lv Zheng
2026-01-29  6:09   ` [PATCH v1.1 6/7] spacemit/t100: Add global filter " Lv Zheng
2026-01-29  6:09   ` [PATCH v1.1 7/7] spacemit/t100: Add SpacemiT T100 IOATC HPM support Lv Zheng
2026-02-06 10:44   ` [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU Krzysztof Kozlowski
2026-02-04  9:08 ` [PATCH v3 0/8] " Lv Zheng
2026-02-06 10:44   ` Krzysztof Kozlowski
2026-02-07  3:41     ` Lv Zheng
2026-02-13 22:21       ` Yixun Lan
2026-02-27  5:55         ` Lv Zheng
     [not found] ` <cover.1770195980.git.lv.zheng@linux.spacemit.com>
2026-02-04  9:08   ` [PATCH v3 1/8] iommu/riscv: Enable IOMMU DMA mapping support Lv Zheng
2026-02-04  9:08   ` [PATCH v3 2/8] iommu/riscv: Fix WSI mode IRQ number handling Lv Zheng
2026-02-04 17:20     ` Andrew Jones
2026-02-05  3:52       ` Lv Zheng
2026-02-05 15:04         ` Andrew Jones
2026-02-06  1:36           ` Lv Zheng
2026-02-04  9:09   ` [PATCH v3 3/8] iommu/riscv: Add HPM support for performance monitoring Lv Zheng
2026-02-04 18:39     ` Andrew Jones
2026-02-05  2:11       ` Zong Li
2026-02-05  3:35       ` Lv Zheng
2026-02-05  3:47         ` Zong Li
2026-02-05  6:11           ` Lv Zheng
2026-02-05 15:23             ` Andrew Jones
2026-02-06  3:42               ` Lv Zheng
2026-02-06 15:09                 ` Andrew Jones
2026-02-07  2:11                   ` Zong Li
2026-02-04  9:09   ` [PATCH v3 4/8] dt-bindings: iommu: Add spacemit/t100 features Lv Zheng
2026-02-04 17:37     ` Conor Dooley
2026-02-05  3:11       ` Lv Zheng
2026-02-05 18:24         ` Conor Dooley
2026-02-06  1:33           ` Lv Zheng
2026-02-06 10:24             ` Conor Dooley
2026-02-07  4:24               ` Lv Zheng
2026-02-07 14:55                 ` Conor Dooley
2026-02-04  9:09   ` [PATCH v3 5/8] riscv/iommu: Add vendor event support for RISC-V IOMMU HPM Lv Zheng
2026-02-04  9:09   ` [PATCH v3 6/8] spacemit/t100: Add global filter awareness " Lv Zheng
2026-02-04  9:09   ` [PATCH v3 7/8] spacemit/t100: Add SpacemiT T100 IOATC HPM support Lv Zheng
2026-02-04  9:09   ` [PATCH v3 8/8] perf vendor events riscv:: Add support for spacemit,riscv-iommu HPM aliasing Lv Zheng
2026-02-04 17:38     ` Conor Dooley
2026-02-05  3:22       ` Lv Zheng
2026-02-05  9:09 ` [PATCH v4 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU Lv Zheng
2026-02-06 10:46   ` Krzysztof Kozlowski
2026-02-07  3:54     ` Lv Zheng
     [not found] ` <cover.1770281596.git.lv.zheng@linux.spacemit.com>
2026-02-05  9:10   ` [PATCH v4 1/7] iommu/riscv: Enable IOMMU DMA mapping support Lv Zheng
2026-02-05  9:10   ` [PATCH v4 2/7] iommu/riscv: Add HPM support for performance monitoring Lv Zheng
2026-02-05  9:10   ` [PATCH v4 3/7] dt-bindings: iommu: Add spacemit/t100 features Lv Zheng
2026-02-05 18:26     ` Conor Dooley
2026-02-06  3:44       ` Lv Zheng
2026-02-05  9:10   ` [PATCH v4 4/7] iommu/riscv: Add vendor event support for RISC-V IOMMU HPM Lv Zheng
2026-02-05  9:11   ` [PATCH v4 5/7] spacemit/t100: Add global filter awareness " Lv Zheng
2026-02-05  9:11   ` [PATCH v4 6/7] spacemit/t100: Add SpacemiT T100 IOATC HPM support Lv Zheng
2026-02-05  9:11   ` [PATCH v4 7/7] perf vendor events riscv:: Add support for spacemit,riscv-iommu HPM aliasing Lv Zheng

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=2f1f48c6-ad75-4e7d-89a2-c93bb1c1d067@arm.com \
    --to=robin.murphy@arm.com \
    --cc=alex@ghiti.fr \
    --cc=aou@eecs.berkeley.edu \
    --cc=conor+dt@kernel.org \
    --cc=conor@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=iommu@lists.linux.dev \
    --cc=joey.li@spacemit.com \
    --cc=joro@8bytes.org \
    --cc=krzk+dt@kernel.org \
    --cc=linux-perf-users@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=lv.zheng@spacemit.com \
    --cc=palmer@dabbelt.com \
    --cc=pjw@kernel.org \
    --cc=robh@kernel.org \
    --cc=spacemit@lists.linux.dev \
    --cc=tjeznach@rivosinc.com \
    --cc=will@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox