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Tue, 22 Oct 2024 13:20:57 +0000 Message-ID: <2f83a298-8212-4d7b-8fa8-b03c939e054b@intel.com> Date: Tue, 22 Oct 2024 21:25:33 +0800 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/9] iommu/vt-d: Let intel_pasid_tear_down_entry() return pasid entry To: Baolu Lu , , , , CC: , , , , , , , References: <20241018055402.23277-1-yi.l.liu@intel.com> <20241018055402.23277-4-yi.l.liu@intel.com> <521b4f3e-1979-46f5-bfad-87951db2b6ed@intel.com> <9d726285-730a-400d-8d45-f494b2c62205@linux.intel.com> <965fe7e8-9a23-48a7-a84d-819f0c330cde@linux.intel.com> Content-Language: en-US From: Yi Liu In-Reply-To: <965fe7e8-9a23-48a7-a84d-819f0c330cde@linux.intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: SG2PR01CA0198.apcprd01.prod.exchangelabs.com (2603:1096:4:189::7) To DS0PR11MB7529.namprd11.prod.outlook.com (2603:10b6:8:141::20) Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR11MB7529:EE_|CO1PR11MB4994:EE_ X-MS-Office365-Filtering-Correlation-Id: 900bdbee-462b-47e1-4e9f-08dcf29c5d7e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|366016|1800799024; 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Letting intel_pasid_tear_down_entry() return the >>>>>>>> pasid >>>>>>>> entry can avoid duplicate codes to get the pasid entry. No functional >>>>>>>> change is intended. >>>>>>>> >>>>>>>> Signed-off-by: Yi Liu >>>>>>>> --- >>>>>>>>   drivers/iommu/intel/pasid.c | 11 ++++++++--- >>>>>>>>   drivers/iommu/intel/pasid.h |  5 +++-- >>>>>>>>   2 files changed, 11 insertions(+), 5 deletions(-) >>>>>>>> >>>>>>>> diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/ >>>>>>>> pasid.c >>>>>>>> index 2898e7af2cf4..336f9425214c 100644 >>>>>>>> --- a/drivers/iommu/intel/pasid.c >>>>>>>> +++ b/drivers/iommu/intel/pasid.c >>>>>>>> @@ -239,9 +239,12 @@ devtlb_invalidation_with_pasid(struct >>>>>>>> intel_iommu *iommu, >>>>>>>>   /* >>>>>>>>    * Caller can request to drain PRQ in this helper if it hasn't >>>>>>>> done so, >>>>>>>>    * e.g. in a path which doesn't follow remove_dev_pasid(). >>>>>>>> + * Return the pasid entry pointer if the entry is found or NULL if no >>>>>>>> + * entry found. >>>>>>>>    */ >>>>>>>> -void intel_pasid_tear_down_entry(struct intel_iommu *iommu, struct >>>>>>>> device *dev, >>>>>>>> -                 u32 pasid, u32 flags) >>>>>>>> +struct pasid_entry * >>>>>>>> +intel_pasid_tear_down_entry(struct intel_iommu *iommu, struct >>>>>>>> device *dev, >>>>>>>> +                u32 pasid, u32 flags) >>>>>>>>   { >>>>>>>>       struct pasid_entry *pte; >>>>>>>>       u16 did, pgtt; >>>>>>>> @@ -250,7 +253,7 @@ void intel_pasid_tear_down_entry(struct >>>>>>>> intel_iommu *iommu, struct device *dev, >>>>>>>>       pte = intel_pasid_get_entry(dev, pasid); >>>>>>>>       if (WARN_ON(!pte) || !pasid_pte_is_present(pte)) { >>>>>>>>           spin_unlock(&iommu->lock); >>>>>>>> -        return; >>>>>>>> +        goto out; >>>>>>> >>>>>>> The pasid table entry is protected by iommu->lock. It's  not reasonable >>>>>>> to return the pte pointer which is beyond the lock protected range. >>>>>> >>>>>> Per my understanding, the iommu->lock protects the content of the entry, >>>>>> so the modifications to the entry need to hold it. While, it looks not >>>>>> necessary to protect the pasid entry pointer itself. The pasid table >>>>>> should >>>>>> exist during device probe and release. is it? >>>>> >>>>> The pattern of the code that modifies a pasid table entry is, >>>>> >>>>>      spin_lock(&iommu->lock); >>>>>      pte = intel_pasid_get_entry(dev, pasid); >>>>>      ... modify the pasid table entry ... >>>>>      spin_unlock(&iommu->lock); >>>>> >>>>> Returning the pte pointer to the caller introduces a potential race >>>>> condition. If the caller subsequently modifies the pte without re- >>>>> acquiring the spin lock, there's a risk of data corruption or >>>>> inconsistencies. >>>> >>>> it appears that we are on the same page about if pte pointer needs to be >>>> protected or not. And I agree the modifications to the pte should be >>>> protected by iommu->lock. If so, will documenting that the caller must >>>> hold >>>> iommu->lock if is tries to modify the content of pte work? Also, it might >>>> be helpful to add lockdep to make sure all the modifications of pte entry >>>> are under protection. >>> >>> People will soon forget about this lock and may modify the returned pte >>> pointer without locking, introducing a race condition silently. >>> >>>> Or any suggestion from you given a path that needs to get pte first, check >>>> if it exists and then call intel_pasid_tear_down_entry(). For example the >>>> intel_pasid_setup_first_level() [1], in my series, I need to call the >>>> unlock iommu->lock and call intel_pasid_tear_down_entry() and then lock >>>> iommu->lock and do more modifications on the pasid entry. It would invoke >>>> the intel_pasid_get_entry() twice if no change to >>>> intel_pasid_tear_down_entry(). >>> >>> There is no need to check the present of a pte entry before calling into >>> intel_pasid_tear_down_entry(). The helper will return directly if the >>> pte is not present: >>> >>>          spin_lock(&iommu->lock); >>>          pte = intel_pasid_get_entry(dev, pasid); >>>          if (WARN_ON(!pte) || !pasid_pte_is_present(pte)) { >>>                  spin_unlock(&iommu->lock); >>>                  return; >>>          } >>> >>> Does it work for you? >> >> This is not I'm talking about. My intention is to avoid duplicated >> intel_pasid_get_entry() call when calling intel_pasid_tear_down_entry() in >> intel_pasid_setup_first_level(). Both the two functions call the >> intel_pasid_get_entry() to get pte pointer. So I think it might be good to >> save one of them. > > Then, perhaps you can add a pasid_entry_tear_down() helper which asserts > iommu->lock and call it in both intel_pasid_tear_down_entry() and > intel_pasid_setup_first_level()? hmmm. I still have a doubt. Only part of the intel_pasid_tear_down_entry() holds the iommu->lock. I'm afraid it's uneasy to split the intel_pasid_tear_down_entry() without letting the cache flush code under the iommu->lock. But it seems unnecessary to do cache flush under the iommu->lock. What about your thought? or am I getting you correctly? Also, I suppose this split allows the caller of the new pasid_entry_tear_down() helper to pass in the pte pointer. is it? void intel_pasid_tear_down_entry(struct intel_iommu *iommu, struct device *dev, u32 pasid, bool fault_ignore) { struct pasid_entry *pte; u16 did, pgtt; spin_lock(&iommu->lock); pte = intel_pasid_get_entry(dev, pasid); if (WARN_ON(!pte) || !pasid_pte_is_present(pte)) { spin_unlock(&iommu->lock); return; } did = pasid_get_domain_id(pte); pgtt = pasid_pte_get_pgtt(pte); intel_pasid_clear_entry(dev, pasid, fault_ignore); spin_unlock(&iommu->lock); if (!ecap_coherent(iommu->ecap)) clflush_cache_range(pte, sizeof(*pte)); pasid_cache_invalidation_with_pasid(iommu, did, pasid); if (pgtt == PASID_ENTRY_PGTT_PT || pgtt == PASID_ENTRY_PGTT_FL_ONLY) qi_flush_piotlb(iommu, did, pasid, 0, -1, 0); else iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH); devtlb_invalidation_with_pasid(iommu, dev, pasid); } -- Regards, Yi Liu