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[213.36.7.13]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37189896a9csm10335771f8f.79.2024.08.19.04.37.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 19 Aug 2024 04:37:45 -0700 (PDT) Message-ID: <30489eee-075b-461b-ab43-c8807d667630@freebox.fr> Date: Mon, 19 Aug 2024 13:37:44 +0200 Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] dt-bindings: arm-smmu: Add qcom,last-ctx-bank-reserved To: Rob Herring Cc: Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel , Krzysztof Kozlowski , Conor Dooley , iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bjorn Andersson , Konrad Dybcio , Arnaud Vrac , Pierre-Hugues Husson , Marijn Suijten References: <20240814-smmu-v1-0-3d6c27027d5b@freebox.fr> <20240814-smmu-v1-1-3d6c27027d5b@freebox.fr> <20240818152515.GA104481-robh@kernel.org> Content-Language: en-US From: Marc Gonzalez In-Reply-To: <20240818152515.GA104481-robh@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 18/08/2024 17:25, Rob Herring wrote: > On Wed, Aug 14, 2024 at 03:59:55PM +0200, Marc Gonzalez wrote: > >> On qcom msm8998, writing to the last context bank of lpass_q6_smmu >> (base address 0x05100000) produces a system freeze & reboot. >> >> Specifically, here: >> >> qsmmu->bypass_cbndx = smmu->num_context_banks - 1; >> arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0); >> >> and here: >> >> arm_smmu_write_context_bank(smmu, i); >> arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT); >> >> It is likely that FW reserves the last context bank for its own use, >> thus a simple work-around would be: DON'T USE IT in Linux. >> >> Signed-off-by: Marc Gonzalez >> --- >> Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 6 ++++++ >> 1 file changed, 6 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >> index 280b4e49f2191..f9b23aef351b0 100644 >> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >> @@ -204,6 +204,12 @@ properties: >> access to SMMU configuration registers. In this case non-secure aliases of >> secure registers have to be used during SMMU configuration. >> >> + qcom,last-ctx-bank-reserved: >> + type: boolean >> + description: >> + FW reserves the last context bank of this SMMU for its own use. >> + If Linux tries to use it, Linux gets nuked. > > How is this Qualcomm specific? Presumably any implementation could do > this if there's no way to properly partition things. Robin? Obviously, there is nothing Qualcomm specific about reserving an SMMU context bank for the FW / hypervisor, other than it appears that qcom is the first to do it; or at least the LPASS SMMU on qcom msm8998 is the first known SMMU where such a work-around is required. What is the correct nomenclature? Can we just drop the vendor prefix if a property is generic across vendors? But does it require a subsystem prefix like "iommu" in order to not clash with generic props in other subsystems? > Also, this property isn't very flexible. What happens when it is not the > last bank or more than 1 bank reserved? This should probably be a mask > instead. OK, I'm getting conflicting requests here. Bjorn has recommended dropping the property altogether: > It also seems, as the different SMMUs in this platform behave > differently it might be worth giving them further specific compatibles, > in which case we could just check if it's the qcom,msm8998-lpass-smmu, > instead of inventing a property for this quirk. I'll send a patch series in line with Bjorn's request. Regards