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15 Apr 2020 18:46:22 -0700 Subject: Re: [PATCH v2 5/7] iommu/vt-d: Save prq descriptors in an internal list To: "Tian, Kevin" , Joerg Roedel References: <20200415052542.30421-1-baolu.lu@linux.intel.com> <20200415052542.30421-6-baolu.lu@linux.intel.com> From: Lu Baolu Message-ID: <399dd037-b32e-30a7-013c-b68e9a3bbc7a@linux.intel.com> Date: Thu, 16 Apr 2020 09:46:21 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US Cc: "Raj, Ashok" , "linux-kernel@vger.kernel.org" , "iommu@lists.linux-foundation.org" X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On 2020/4/15 17:30, Tian, Kevin wrote: >> From: Lu Baolu >> Sent: Wednesday, April 15, 2020 1:26 PM >> >> Currently, the page request interrupt thread handles the page >> requests in the queue in this way: >> >> - Clear PPR bit to ensure new interrupt could come in; >> - Read and record the head and tail registers; >> - Handle all descriptors between head and tail; >> - Write tail to head register. >> >> This might cause some descriptors to be handles multiple times. >> An example sequence: >> >> - Thread A got scheduled with PRQ_1 and PRQ_2 in the queue; >> - Thread A clear the PPR bit and record the head and tail; >> - A new PRQ_3 comes and Thread B gets scheduled; >> - Thread B record the head and tail which includes PRQ_1 >> and PRQ_2. > I may overlook something but isn't the prq interrupt thread > per iommu then why would two prq threads contend here? The prq interrupt could be masked by the PPR (Pending Page Request) bit in Page Request Status Register. In the interrupt handling thread once this bit is clear, new prq interrupts are allowed to be generated. So, if a page request is in process and the PPR bit is cleared, another page request from any devices under the same iommu could trigger another interrupt thread. Best regards, baolu _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu