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Date: Mon, 22 Aug 2022 11:06:43 +0100
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Subject: Re: [PATCH] mmc: sdhci-xenon: Fix 2G limitation on AC5 SoC
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To: Christoph Hellwig <hch@infradead.org>,
 Vadym Kochan <vadym.kochan@plvision.eu>
Cc: Adrian Hunter <adrian.hunter@intel.com>,
 Florian Fainelli <f.fainelli@gmail.com>, Hu Ziji <huziji@marvell.com>,
 Ulf Hansson <ulf.hansson@linaro.org>, linux-mmc@vger.kernel.org,
 linux-kernel@vger.kernel.org, Elad Nachman <enachman@marvell.com>,
 iommu@lists.linux.dev, Mickey Rachamim <mickeyr@marvell.com>
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From: Robin Murphy <robin.murphy@arm.com>
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On 2022-08-21 07:17, Christoph Hellwig wrote:
> On Thu, Aug 18, 2022 at 03:07:40PM +0300, Vadym Kochan wrote:
>> It works with the following changes:
>>
>>      #1 dma-ranges = <0x0 0x0 0x2 0x0 0x0 0x80000000>;
>>
>>      #3 swiotlb="force"
>>
>> Is it OK to force the memory allocation from the start for the swiotlb ?
> 
> It should be ok, but isn't really optimal.
> 
> I wonder if we should just allow DT to specify the swiotlb buffer
> location.  Basically have yet another RESERVEDMEM_OF_DECLARE variant
> for it, which shouldn't be all that much work except for figuring
> out the interaction with the various kernel command line options.

We already have all the information we need in the DT (and ACPI), the 
arm64 init code just needs to do a better job of interpreting it 
properly. I'll see what I can come up with once I've finished what I'm 
currently tied up in.

Thanks,
Robin.