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Wed, 20 Jan 2021 05:18:51 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 13973C433CA; Wed, 20 Jan 2021 05:18:51 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id 52F8BC43464; Wed, 20 Jan 2021 05:18:50 +0000 (UTC) MIME-Version: 1.0 Date: Wed, 20 Jan 2021 10:48:50 +0530 From: Sai Prakash Ranjan To: Will Deacon , Robin Murphy , Joerg Roedel , Jordan Crouse , Rob Clark , Akhil P Oommen , isaacm@codeaurora.org Subject: Re: [PATCH 0/3] iommu/drm/msm: Allow non-coherent masters to use system cache In-Reply-To: References: Message-ID: <3e6ec220c07bcf91fae0985e1798f7a1@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Cc: Sean Paul , David Airlie , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, iommu@lists.linux-foundation.org, Kristian H Kristensen , Daniel Vetter , freedreno , linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On 2021-01-11 19:45, Sai Prakash Ranjan wrote: > commit ecd7274fb4cd ("iommu: Remove unused IOMMU_SYS_CACHE_ONLY flag") > removed unused IOMMU_SYS_CACHE_ONLY prot flag and along with it went > the memory type setting required for the non-coherent masters to use > system cache. Now that system cache support for GPU is added, we will > need to set the right PTE attribute for GPU buffers to be sys cached. > Without this, the system cache lines are not allocated for GPU. > > So the patches in this series introduces a new prot flag IOMMU_LLC, > renames IO_PGTABLE_QUIRK_ARM_OUTER_WBWA to IO_PGTABLE_QUIRK_PTW_LLC > and makes GPU the user of this protection flag. > > The series slightly depends on following 2 patches posted earlier and > is based on msm-next branch: > * https://lore.kernel.org/patchwork/patch/1363008/ > * https://lore.kernel.org/patchwork/patch/1363010/ > > Sai Prakash Ranjan (3): > iommu/io-pgtable: Rename last-level cache quirk to > IO_PGTABLE_QUIRK_PTW_LLC > iommu/io-pgtable-arm: Add IOMMU_LLC page protection flag > drm/msm: Use IOMMU_LLC page protection flag to map gpu buffers > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +++ > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- > drivers/gpu/drm/msm/msm_iommu.c | 3 +++ > drivers/gpu/drm/msm/msm_mmu.h | 4 ++++ > drivers/iommu/io-pgtable-arm.c | 9 ++++++--- > include/linux/io-pgtable.h | 6 +++--- > include/linux/iommu.h | 6 ++++++ > 7 files changed, 26 insertions(+), 7 deletions(-) > > > base-commit: 00fd44a1a4700718d5d962432b55c09820f7e709 Gentle Ping! Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu