From: Lu Baolu <baolu.lu@linux.intel.com>
To: "Liu, Yi L" <yi.l.liu@intel.com>, Joerg Roedel <joro@8bytes.org>,
David Woodhouse <dwmw2@infradead.org>,
Alex Williamson <alex.williamson@redhat.com>
Cc: "Tian, Kevin" <kevin.tian@intel.com>,
"Raj, Ashok" <ashok.raj@intel.com>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"Kumar, Sanjay K" <sanjay.k.kumar@intel.com>,
"iommu@lists.linux-foundation.org"
<iommu@lists.linux-foundation.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"Sun, Yi Y" <yi.y.sun@intel.com>
Subject: Re: [PATCH v4 0/7] Use 1st-level for IOVA translation
Date: Sat, 21 Dec 2019 11:14:35 +0800 [thread overview]
Message-ID: <434d7478-1ed3-1962-ff9d-1b37d0c44b9c@linux.intel.com> (raw)
In-Reply-To: <A2975661238FB949B60364EF0F2C25743A13A364@SHSMSX104.ccr.corp.intel.com>
Hi again,
On 2019/12/20 19:50, Liu, Yi L wrote:
> 3) Per VT-d spec, FLPT has canonical requirement to the input
> addresses. So I'd suggest to add some enhance regards to it.
> Please refer to chapter 3.6:-).
>
> 3.6 First-Level Translation
> First-level translation restricts the input-address to a canonical address (i.e., address bits 63:N have
> the same value as address bit [N-1], where N is 48-bits with 4-level paging and 57-bits with 5-level
> paging). Requests subject to first-level translation by remapping hardware are subject to canonical
> address checking as a pre-condition for first-level translation, and a violation is treated as a
> translation-fault.
It seems to be a conflict at bit 63. It should be the same as bit[N-1]
according to the canonical address requirement; but it is also used as
the XD control. Any thought?
Best regards,
baolu
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next prev parent reply other threads:[~2019-12-21 3:14 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-19 3:16 [PATCH v4 0/7] Use 1st-level for IOVA translation Lu Baolu
2019-12-19 3:16 ` [PATCH v4 1/7] iommu/vt-d: Identify domains using first level page table Lu Baolu
2019-12-19 3:16 ` [PATCH v4 2/7] iommu/vt-d: Add set domain DOMAIN_ATTR_NESTING attr Lu Baolu
2019-12-19 3:16 ` [PATCH v4 3/7] iommu/vt-d: Add PASID_FLAG_FL5LP for first-level pasid setup Lu Baolu
2019-12-19 3:16 ` [PATCH v4 4/7] iommu/vt-d: Setup pasid entries for iova over first level Lu Baolu
2019-12-20 11:44 ` Liu, Yi L
2019-12-21 2:26 ` Lu Baolu
2019-12-19 3:16 ` [PATCH v4 5/7] iommu/vt-d: Flush PASID-based iotlb " Lu Baolu
2019-12-19 3:16 ` [PATCH v4 6/7] iommu/vt-d: Use " Lu Baolu
2019-12-19 3:16 ` [PATCH v4 7/7] iommu/vt-d: debugfs: Add support to show page table internals Lu Baolu
2019-12-20 11:50 ` [PATCH v4 0/7] Use 1st-level for IOVA translation Liu, Yi L
2019-12-21 2:51 ` Lu Baolu
2019-12-21 3:14 ` Lu Baolu [this message]
2019-12-22 7:00 ` Lu Baolu
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