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Thu, 09 Apr 2020 06:14:40 -0400 X-MC-Unique: 08xiuF_KNYOglmQhzs9DPA-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id A787B149C0; Thu, 9 Apr 2020 10:14:38 +0000 (UTC) Received: from [10.36.115.53] (ovpn-115-53.ams2.redhat.com [10.36.115.53]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 231CAD766F; Thu, 9 Apr 2020 10:14:32 +0000 (UTC) Subject: Re: [PATCH v11 08/10] iommu/vt-d: Cache virtual command capability register To: Jacob Pan , Lu Baolu , iommu@lists.linux-foundation.org, LKML , Joerg Roedel , David Woodhouse , Jean-Philippe Brucker References: <1585939334-21396-1-git-send-email-jacob.jun.pan@linux.intel.com> <1585939334-21396-9-git-send-email-jacob.jun.pan@linux.intel.com> From: Auger Eric Message-ID: <43e7452c-dea8-934c-105e-05798cb1d225@redhat.com> Date: Thu, 9 Apr 2020 12:14:31 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <1585939334-21396-9-git-send-email-jacob.jun.pan@linux.intel.com> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 Cc: "Tian, Kevin" , Raj Ashok , Alex Williamson , Jonathan Cameron X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" Hi Jacob, On 4/3/20 8:42 PM, Jacob Pan wrote: > Virtual command registers are used in the guest only, to prevent > vmexit cost, we cache the capability and store it during initialization. > > Signed-off-by: Jacob Pan > Reviewed-by: Eric Auger > Reviewed-by: Lu Baolu nit: following Joerg's comment on 02/10, may be worth squashing it into the patch that uses it (10/10) Thanks Eric > > --- > v7 Reviewed by Eric & Baolu > --- > > Signed-off-by: Jacob Pan > --- > drivers/iommu/dmar.c | 1 + > include/linux/intel-iommu.h | 5 +++++ > 2 files changed, 6 insertions(+) > > diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c > index 4d6b7b5b37ee..3b36491c8bbb 100644 > --- a/drivers/iommu/dmar.c > +++ b/drivers/iommu/dmar.c > @@ -963,6 +963,7 @@ static int map_iommu(struct intel_iommu *iommu, u64 phys_addr) > warn_invalid_dmar(phys_addr, " returns all ones"); > goto unmap; > } > + iommu->vccap = dmar_readq(iommu->reg + DMAR_VCCAP_REG); > > /* the registers might be more than one page */ > map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap), > diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h > index f775bb825343..e02a96848586 100644 > --- a/include/linux/intel-iommu.h > +++ b/include/linux/intel-iommu.h > @@ -194,6 +194,9 @@ > #define ecap_max_handle_mask(e) ((e >> 20) & 0xf) > #define ecap_sc_support(e) ((e >> 7) & 0x1) /* Snooping Control */ > > +/* Virtual command interface capability */ > +#define vccap_pasid(v) ((v & DMA_VCS_PAS)) /* PASID allocation */ > + > /* IOTLB_REG */ > #define DMA_TLB_FLUSH_GRANU_OFFSET 60 > #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60) > @@ -287,6 +290,7 @@ > > /* PRS_REG */ > #define DMA_PRS_PPR ((u32)1) > +#define DMA_VCS_PAS ((u64)1) > > #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \ > do { \ > @@ -562,6 +566,7 @@ struct intel_iommu { > u64 reg_size; /* size of hw register set */ > u64 cap; > u64 ecap; > + u64 vccap; > u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */ > raw_spinlock_t register_lock; /* protect register handling */ > int seq_id; /* sequence id of the iommu */ > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu