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([2a02:810d:15c0:828:183b:950f:b4d5:135a]) by smtp.gmail.com with ESMTPSA id lc11-20020a170906f90b00b0096637a19dccsm939236ejb.210.2023.05.07.01.20.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 07 May 2023 01:20:39 -0700 (PDT) Message-ID: <4a563d96-ec59-7db3-d288-1ba3bb9d8eb7@linaro.org> Date: Sun, 7 May 2023 10:20:38 +0200 Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.1 Subject: Re: [PATCH v3 05/12] dt-bindings: display/msm: Add SM6375 MDSS Content-Language: en-US To: Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev References: <20230411-topic-straitlagoon_mdss-v3-0-9837d6b3516d@linaro.org> <20230411-topic-straitlagoon_mdss-v3-5-9837d6b3516d@linaro.org> From: Krzysztof Kozlowski In-Reply-To: <20230411-topic-straitlagoon_mdss-v3-5-9837d6b3516d@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 05/05/2023 23:40, Konrad Dybcio wrote: > Document the SM6375 MDSS. > > Signed-off-by: Konrad Dybcio > --- > .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +++++++++++++++++++++ > 1 file changed, 216 insertions(+) > Thank you for your patch. There is something to discuss/improve. > + > +examples: > + - | > + #include > + #include > + #include > + #include > + #include > + > + display-subsystem@5e00000 { > + compatible = "qcom,sm6375-mdss"; > + reg = <0x05e00000 0x1000>; > + reg-names = "mdss"; > + > + power-domains = <&dispcc MDSS_GDSC>; > + > + clocks = <&gcc GCC_DISP_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>; > + clock-names = "iface", "ahb", "core"; > + > + interrupts = ; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + iommus = <&apps_smmu 0x820 0x2>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + display-controller@5e01000 { > + compatible = "qcom,sm6375-dpu"; > + reg = <0x05e01000 0x8e030>, > + <0x05eb0000 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_ROT_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, > + <&gcc GCC_DISP_THROTTLE_CORE_CLK>; > + clock-names = "iface", > + "bus", > + "core", > + "lut", > + "rot", > + "vsync", > + "throttle"; Are you sure you have clocks in correct order? I see warnings... Best regards, Krzysztof